dev/hatm/if_hatm.c

514 	WRITE4(sc, HE_REGO_RESET_CNTL, 0x00);
516 	WRITE4(sc, HE_REGO_RESET_CNTL, 0xff);
549 		WRITE4(sc, HE_REGO_HOST_CNTL, v);
588 	WRITE4(sc, HE_REGO_LB_SWAP, v);
607 	WRITE4(sc, HE_REGO_HOST_CNTL, val);
612 		WRITE4(sc, HE_REGO_HOST_CNTL, val | readtab[i]);
619 		WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++] |
623 		WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++] |
630 	WRITE4(sc, HE_REGO_HOST_CNTL, val);
636 		WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++]);
642 		WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++]);
646 	WRITE4(sc, HE_REGO_HOST_CNTL, val | clocktab[j++]);
734 	WRITE4(sc, HE_REGO_IRQ_BASE(group), 0);
735 	WRITE4(sc, HE_REGO_IRQ_HEAD(group), 0);
736 	WRITE4(sc, HE_REGO_IRQ_CNTL(group), 0);
737 	WRITE4(sc, HE_REGO_IRQ_DATA(group), 0);
763 	WRITE4(sc, HE_REGO_IRQ_BASE(group), q->mem.paddr);
764 	WRITE4(sc, HE_REGO_IRQ_HEAD(group),
767 	WRITE4(sc, HE_REGO_IRQ_CNTL(group), q->line);
768 	WRITE4(sc, HE_REGO_IRQ_DATA(group), 0);
805 	WRITE4(sc, HE_REGO_TSRB_BA, sc->tsrb);
806 	WRITE4(sc, HE_REGO_TSRC_BA, sc->tsrc);
807 	WRITE4(sc, HE_REGO_TSRD_BA, sc->tsrd);
808 	WRITE4(sc, HE_REGO_TMABR_BA, tabr);
809 	WRITE4(sc, HE_REGO_TPD_BA, mtpd);
811 	WRITE4(sc, HE_REGO_RCMRSRB_BA, sc->rsrb);
812 	WRITE4(sc, HE_REGO_RCMLBM_BA, mlbm);
813 	WRITE4(sc, HE_REGO_RCMABR_BA, rabr);
850 	WRITE4(sc, HE_REGO_RLBF_H(num), lbufd_index);
869 	WRITE4(sc, HE_REGO_RLBF_T(num), lbufd_index - 2);
870 	WRITE4(sc, HE_REGO_RLBF_C(num), numbuffs);
903 	WRITE4(sc, HE_REGO_TLBF_H, lbufd_index);
921 	WRITE4(sc, HE_REGO_TLBF_T, lbufd_index - 1);
935 			WRITE4(sc, HE_REGO_INMQ_S(n), 0x10*n+0x000f);
936 			WRITE4(sc, HE_REGO_INMQ_L(n), 0x10*n+0x200f);
940 			WRITE4(sc, HE_REGO_INMQ_S(n), n);
941 			WRITE4(sc, HE_REGO_INMQ_L(n), n+0x8);
1118 	WRITE4(sc, HE_REGO_RBP_S(large, group), 0);
1119 	WRITE4(sc, HE_REGO_RBP_T(large, group), 0);
1120 	WRITE4(sc, HE_REGO_RBP_QI(large, group), 1);
1121 	WRITE4(sc, HE_REGO_RBP_BL(large, group), 0);
1143 	WRITE4(sc, HE_REGO_RBP_S(large, group), q->mem.paddr);
1144 	WRITE4(sc, HE_REGO_RBP_T(large, group), 0);
1145 	WRITE4(sc, HE_REGO_RBP_QI(large, group),
1149 	WRITE4(sc, HE_REGO_RBP_BL(large, group), (q->bsize >> 2) & ~1);
1158 	WRITE4(sc, HE_REGO_RBRQ_ST(group), 0);
1159 	WRITE4(sc, HE_REGO_RBRQ_H(group), 0);
1160 	WRITE4(sc, HE_REGO_RBRQ_Q(group), (1 << HE_REGS_RBRQ_THRESH));
1161 	WRITE4(sc, HE_REGO_RBRQ_I(group), 0);
1180 	WRITE4(sc, HE_REGO_RBRQ_ST(group), rq->mem.paddr);
1181 	WRITE4(sc, HE_REGO_RBRQ_H(group), 0);
1182 	WRITE4(sc, HE_REGO_RBRQ_Q(group),
1185 	WRITE4(sc, HE_REGO_RBRQ_I(group),
1196 	WRITE4(sc, HE_REGO_TBRQ_B_T(group), 0);
1197 	WRITE4(sc, HE_REGO_TBRQ_H(group), 0);
1198 	WRITE4(sc, HE_REGO_TBRQ_S(group), 0);
1199 	WRITE4(sc, HE_REGO_TBRQ_THRESH(group), 1);
1218 	WRITE4(sc, HE_REGO_TBRQ_B_T(group), tq->mem.paddr);
1219 	WRITE4(sc, HE_REGO_TBRQ_H(group), 0);
1220 	WRITE4(sc, HE_REGO_TBRQ_S(group), tq->size - 1);
1221 	WRITE4(sc, HE_REGO_TBRQ_THRESH(group), tq->thresh);
1238 	WRITE4(sc, HE_REGO_TPDRQ_H, tq->mem.paddr);
1239 	WRITE4(sc, HE_REGO_TPDRQ_T, 0);
1240 	WRITE4(sc, HE_REGO_TPDRQ_S, tq->size - 1);
1618 	WRITE4(sc, HE_REGO_SUNI + 4 * reg, regval);
1997 		WRITE4(sc, HE_REGO_SDRAM_CNTL, HE_REGM_SDRAM_64BIT);
1999 		WRITE4(sc, HE_REGO_SDRAM_CNTL, 0);
2005 	WRITE4(sc, HE_REGO_LB_SWAP, v);
2013 	WRITE4(sc, HE_REGO_GRP_1_0_MAP, 0);
2014 	WRITE4(sc, HE_REGO_GRP_3_2_MAP, 0);
2015 	WRITE4(sc, HE_REGO_GRP_5_4_MAP, 0);
2016 	WRITE4(sc, HE_REGO_GRP_7_6_MAP, 0);
2026 	WRITE4(sc, HE_REGO_HOST_CNTL, v);
2068 		WRITE4(sc, HE_REGO_LBARB,
2078 		WRITE4(sc, HE_REGO_SDRAMCON,
2084 		WRITE4(sc, HE_REGO_RCMCONFIG,
2088 		WRITE4(sc, HE_REGO_TCMCONFIG,
2093 		WRITE4(sc, HE_REGO_LBARB,
2103 		WRITE4(sc, HE_REGO_SDRAMCON,
2108 		WRITE4(sc, HE_REGO_RCMCONFIG,
2112 		WRITE4(sc, HE_REGO_TCMCONFIG,
2117 	WRITE4(sc, HE_REGO_LBCONFIG, (sc->cells_per_lbuf * 48));
2119 	WRITE4(sc, HE_REGO_RLBC_H, 0);
2120 	WRITE4(sc, HE_REGO_RLBC_T, 0);
2121 	WRITE4(sc, HE_REGO_RLBC_H2, 0);
2123 	WRITE4(sc, HE_REGO_RXTHRSH, 512);
2124 	WRITE4(sc, HE_REGO_LITHRSH, 256);
2126 	WRITE4(sc, HE_REGO_RLBF0_C, sc->r0_numbuffs);
2127 	WRITE4(sc, HE_REGO_RLBF1_C, sc->r1_numbuffs);
2130 		WRITE4(sc, HE_REGO_RCCONFIG,
2134 		WRITE4(sc, HE_REGO_TXCONFIG,
2139 		WRITE4(sc, HE_REGO_RCCONFIG,
2144 		WRITE4(sc, HE_REGO_TXCONFIG,
2151 	WRITE4(sc, HE_REGO_TXAAL5_PROTO, 0);
2154 		WRITE4(sc, HE_REGO_RHCONFIG,
2159 		WRITE4(sc, HE_REGO_RHCONFIG,
2177 	WRITE4(sc, HE_REGO_MCC, 0);
2178 	WRITE4(sc, HE_REGO_OEC, 0);
2179 	WRITE4(sc, HE_REGO_DCC, 0);
2180 	WRITE4(sc, HE_REGO_CEC, 0);
2224 	WRITE4(sc, HE_REGO_UBUFF_BA, (sc->he622 ? 0x104780 : 0x800));
2231 	WRITE4(sc, HE_REGO_HSP_BA, sc->hsp_mem.paddr);
2243 	WRITE4(sc, HE_REGO_RCCONFIG, v);
2296 	WRITE4(sc, HE_REGO_RCCONFIG, v);
2298 	WRITE4(sc, HE_REGO_RHCONFIG, (0x2 << HE_REGS_RHCONFIG_PTMR_PRE));
2304 	WRITE4(sc, HE_REGO_HOST_CNTL, v);