dev/ep/if_ep.c

405 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
420 	CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
421 	CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
430 	CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | 0xff);
432 	CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK | S_5_INTS);
433 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);
436 		CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
439 		CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
446 		CSR_WRITE_2(sc, EP_COMMAND, TX_PLL_ENABLE);
447 	CSR_WRITE_2(sc, EP_COMMAND, RX_ENABLE);
448 	CSR_WRITE_2(sc, EP_COMMAND, TX_ENABLE);
462 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
463 	CSR_WRITE_2(sc, EP_COMMAND, SET_TX_START_THRESH | 16);
502 		CSR_WRITE_2(sc, EP_COMMAND, TX_PLL_ENABLE);
522 		CSR_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | (len + pad + 4));
530 		CSR_WRITE_2(sc, EP_COMMAND,
582 			CSR_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | 8);
616 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK);	/* disable all Ints */
623 		CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | (status & S_MASK));
677 					CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
691 					CSR_WRITE_2(sc, EP_COMMAND, TX_ENABLE);
697 						CSR_WRITE_2(sc, EP_COMMAND,
710 	CSR_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH);	/* ACK int Latch */
716 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);
829 		CSR_WRITE_2(sc, EP_COMMAND,
833 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
851 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
855 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
865 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
875 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
891 			CSR_WRITE_2(sc, EP_COMMAND, START_TRANSCEIVER);
1010 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISABLE);
1011 	CSR_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
1014 	CSR_WRITE_2(sc, EP_COMMAND, TX_DISABLE);
1015 	CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
1018 	CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
1020 	CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
1023 	CSR_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH);
1024 	CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK);
1025 	CSR_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK);
1026 	CSR_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER);