Lines Matching refs:_n
90 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
180 #define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n))
204 /* High credit registers where _n can be 0 or 1. */
205 #define E1000_I210_TQAVHC(_n) (0x300C + 0x40 * (_n))
209 /* Queues priority masks where _n and _p can be 0-3. */
210 #define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * (_n)))
211 /* QAV Tx mode control registers where _n can be 0 or 1. */
212 #define E1000_I210_TQAVCC(_n) (0x3004 + 0x40 * (_n))
220 #define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n)))
222 /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */
223 #define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * (_n)))
230 * Note: "_n" is the queue number of the register to be written to.
235 #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
236 (0x0C000 + ((_n) * 0x40)))
237 #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
238 (0x0C004 + ((_n) * 0x40)))
239 #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
240 (0x0C008 + ((_n) * 0x40)))
241 #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
242 (0x0C00C + ((_n) * 0x40)))
243 #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
244 (0x0C010 + ((_n) * 0x40)))
245 #define E1000_RXCTL(_n) ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
246 (0x0C014 + ((_n) * 0x40)))
247 #define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
248 #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
249 (0x0C018 + ((_n) * 0x40)))
250 #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
251 (0x0C028 + ((_n) * 0x40)))
252 #define E1000_RQDPC(_n) ((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \
253 (0x0C030 + ((_n) * 0x40)))
254 #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
255 (0x0E000 + ((_n) * 0x40)))
256 #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
257 (0x0E004 + ((_n) * 0x40)))
258 #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
259 (0x0E008 + ((_n) * 0x40)))
260 #define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
261 (0x0E010 + ((_n) * 0x40)))
262 #define E1000_TXCTL(_n) ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
263 (0x0E014 + ((_n) * 0x40)))
264 #define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)
265 #define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
266 (0x0E018 + ((_n) * 0x40)))
267 #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
268 (0x0E028 + ((_n) * 0x40)))
269 #define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
270 (0x0E038 + ((_n) * 0x40)))
271 #define E1000_TDWBAH(_n) ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
272 (0x0E03C + ((_n) * 0x40)))
273 #define E1000_TARC(_n) (0x03840 + ((_n) * 0x100))
292 #define E1000_PBSLAD(_n) (0x03110 + (0x4 * (_n))) /* Pkt Buffer DWORD */
393 #define E1000_PFVFGPRC(_n) (0x010010 + (0x100 * (_n)))
394 #define E1000_PFVFGPTC(_n) (0x010014 + (0x100 * (_n)))
395 #define E1000_PFVFGORC(_n) (0x010018 + (0x100 * (_n)))
396 #define E1000_PFVFGOTC(_n) (0x010034 + (0x100 * (_n)))
397 #define E1000_PFVFMPRC(_n) (0x010038 + (0x100 * (_n)))
398 #define E1000_PFVFGPRLBC(_n) (0x010040 + (0x100 * (_n)))
399 #define E1000_PFVFGPTLBC(_n) (0x010044 + (0x100 * (_n)))
400 #define E1000_PFVFGORLBC(_n) (0x010048 + (0x100 * (_n)))
401 #define E1000_PFVFGOTLBC(_n) (0x010050 + (0x100 * (_n)))
418 #define E1000_LSECRXOK(_n) (0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */
419 #define E1000_LSECRXINV(_n) (0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */
420 #define E1000_LSECRXNV(_n) (0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */
435 #define E1000_LSECTXKEY0(_n) (0x0B020 + (0x04 * (_n)))
437 #define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n)))
438 #define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */
439 #define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */
440 /* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit
443 #define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
450 #define E1000_IPSRXIPADDR(_n) (0x0B420 + (0x04 * (_n)))
452 #define E1000_IPSRXKEY(_n) (0x0B410 + (0x04 * (_n)))
456 #define E1000_IPSTXKEY(_n) (0x0B460 + (0x04 * (_n)))
506 #define E1000_FHFT(_n) (0x09000 + ((_n) * 0x100))
508 #define E1000_FHFT_EXT(_n) (0x09A00 + ((_n) * 0x100))
514 #define E1000_MDEF(_n) (0x05890 + (4 * (_n)))
571 #define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n)))
572 #define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n)))
573 #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))
574 #define E1000_VFVMBMEM(_n) (0x00800 + (_n))
575 #define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n)))
577 #define E1000_VLVF(_n) (0x05D00 + (4 * (_n)))
578 #define E1000_VMVIR(_n) (0x03700 + (4 * (_n)))
579 #define E1000_DVMOLR(_n) (0x0C038 + (0x40 * (_n))) /* DMA VM offload */
580 #define E1000_VTCTRL(_n) (0x10000 + (0x100 * (_n))) /* VT Control */
607 #define E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
608 #define E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
609 #define E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */
610 #define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
611 #define E1000_TTQF(_n) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
612 #define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
613 #define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
621 #define E1000_RTTDTCRC(_n) (0x3610 + ((_n) * 4))
623 #define E1000_RTTPTCRC(_n) (0x3480 + ((_n) * 4))
625 #define E1000_RTRPTCRC(_n) (0x2480 + ((_n) * 4))
627 #define E1000_RTTDTCRS(_n) (0x3630 + ((_n) * 4))
629 #define E1000_RTTDTCRM(_n) (0x3650 + ((_n) * 4))
631 #define E1000_RTTPTCRS(_n) (0x34A0 + ((_n) * 4))
633 #define E1000_RTTPTCRM(_n) (0x34C0 + ((_n) * 4))
635 #define E1000_RTRPTCRS(_n) (0x24A0 + ((_n) * 4))
637 #define E1000_RTRPTCRM(_n) (0x24C0 + ((_n) * 4))
639 #define E1000_RTTDVMRM(_n) (0x3670 + ((_n) * 4))
641 #define E1000_RTTBCNRM(_n) (0x3690 + ((_n) * 4))