Lines Matching refs:WRITE4
84 #define WRITE4(_sc, _reg, _val) \
280 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1);
313 WRITE4(sc, OPERATION_MODE, reg);
318 WRITE4(sc, OPERATION_MODE, reg);
323 WRITE4(sc, MAC_CONFIGURATION, reg);
328 WRITE4(sc, OPERATION_MODE, reg);
337 WRITE4(sc, MMC_CONTROL, reg);
432 WRITE4(sc, OPERATION_MODE, reg);
434 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);
439 WRITE4(sc, OPERATION_MODE, reg);
445 WRITE4(sc, MAC_CONFIGURATION, reg);
640 WRITE4(sc, MAC_ADDRESS_LOW(0), lo);
641 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi);
642 WRITE4(sc, MAC_FRAME_FILTER, ffval);
644 WRITE4(sc, GMAC_MAC_HTLOW, hash[0]);
645 WRITE4(sc, GMAC_MAC_HTHIGH, hash[1]);
648 WRITE4(sc, HASH_TABLE_REG(i), hash[i]);
833 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);
1183 WRITE4(sc, BUS_MODE, reg);
1201 WRITE4(sc, BUS_MODE, reg);
1208 WRITE4(sc, OPERATION_MODE, reg);
1214 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr);
1215 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr);
1278 WRITE4(sc, GMII_ADDRESS, mii);
1305 WRITE4(sc, GMII_DATA, val);
1306 WRITE4(sc, GMII_ADDRESS, mii);
1367 WRITE4(sc, MAC_CONFIGURATION, reg);