Lines Matching refs:rdev
43 static void rv770_gpu_init(struct radeon_device *rdev);
45 void rv770_fini(struct radeon_device *rdev);
47 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
49 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
51 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
73 for (i = 0; i < rdev->usec_timeout; i++) {
89 int rv770_get_temp(struct radeon_device *rdev)
108 void rv770_pm_misc(struct radeon_device *rdev)
110 int req_ps_idx = rdev->pm.requested_power_state_index;
111 int req_cm_idx = rdev->pm.requested_clock_mode_index;
112 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
119 if (voltage->voltage != rdev->pm.current_vddc) {
120 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
121 rdev->pm.current_vddc = voltage->voltage;
130 static int rv770_pcie_gart_enable(struct radeon_device *rdev)
135 if (rdev->gart.robj == NULL) {
136 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
139 r = radeon_gart_table_vram_pin(rdev);
142 radeon_gart_restore(rdev);
157 if (rdev->family == CHIP_RV740)
163 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
164 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
165 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
169 (u32)(rdev->dummy_page.addr >> 12));
173 r600_pcie_gart_tlb_flush(rdev);
175 (unsigned)(rdev->mc.gtt_size >> 20),
176 (unsigned long long)rdev->gart.table_addr);
177 rdev->gart.ready = true;
181 static void rv770_pcie_gart_disable(struct radeon_device *rdev)
204 radeon_gart_table_vram_unpin(rdev);
207 static void rv770_pcie_gart_fini(struct radeon_device *rdev)
209 radeon_gart_fini(rdev);
210 rv770_pcie_gart_disable(rdev);
211 radeon_gart_table_vram_free(rdev);
215 static void rv770_agp_enable(struct radeon_device *rdev)
242 static void rv770_mc_program(struct radeon_device *rdev)
261 rv515_mc_stop(rdev, &save);
262 if (r600_mc_wait_for_idle(rdev)) {
263 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
268 if (rdev->flags & RADEON_IS_AGP) {
269 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
272 rdev->mc.vram_start >> 12);
274 rdev->mc.gtt_end >> 12);
278 rdev->mc.gtt_start >> 12);
280 rdev->mc.vram_end >> 12);
284 rdev->mc.vram_start >> 12);
286 rdev->mc.vram_end >> 12);
288 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
289 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
290 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
292 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
295 if (rdev->flags & RADEON_IS_AGP) {
296 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
297 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
298 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
304 if (r600_mc_wait_for_idle(rdev)) {
305 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
307 rv515_mc_resume(rdev, &save);
310 rv515_vga_render_disable(rdev);
317 void r700_cp_stop(struct radeon_device *rdev)
319 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
322 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
325 static int rv770_cp_load_microcode(struct radeon_device *rdev)
330 if (!rdev->me_fw || !rdev->pfp_fw)
333 r700_cp_stop(rdev);
346 fw_data = (const __be32 *)rdev->pfp_fw->data;
352 fw_data = (const __be32 *)rdev->me_fw->data;
363 void r700_cp_fini(struct radeon_device *rdev)
365 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
366 r700_cp_stop(rdev);
367 radeon_ring_fini(rdev, ring);
368 radeon_scratch_free(rdev, ring->rptr_save_reg);
374 static void rv770_gpu_init(struct radeon_device *rdev)
399 rdev->config.rv770.tiling_group_size = 256;
400 switch (rdev->family) {
402 rdev->config.rv770.max_pipes = 4;
403 rdev->config.rv770.max_tile_pipes = 8;
404 rdev->config.rv770.max_simds = 10;
405 rdev->config.rv770.max_backends = 4;
406 rdev->config.rv770.max_gprs = 256;
407 rdev->config.rv770.max_threads = 248;
408 rdev->config.rv770.max_stack_entries = 512;
409 rdev->config.rv770.max_hw_contexts = 8;
410 rdev->config.rv770.max_gs_threads = 16 * 2;
411 rdev->config.rv770.sx_max_export_size = 128;
412 rdev->config.rv770.sx_max_export_pos_size = 16;
413 rdev->config.rv770.sx_max_export_smx_size = 112;
414 rdev->config.rv770.sq_num_cf_insts = 2;
416 rdev->config.rv770.sx_num_of_sets = 7;
417 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
418 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
419 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
422 rdev->config.rv770.max_pipes = 2;
423 rdev->config.rv770.max_tile_pipes = 4;
424 rdev->config.rv770.max_simds = 8;
425 rdev->config.rv770.max_backends = 2;
426 rdev->config.rv770.max_gprs = 128;
427 rdev->config.rv770.max_threads = 248;
428 rdev->config.rv770.max_stack_entries = 256;
429 rdev->config.rv770.max_hw_contexts = 8;
430 rdev->config.rv770.max_gs_threads = 16 * 2;
431 rdev->config.rv770.sx_max_export_size = 256;
432 rdev->config.rv770.sx_max_export_pos_size = 32;
433 rdev->config.rv770.sx_max_export_smx_size = 224;
434 rdev->config.rv770.sq_num_cf_insts = 2;
436 rdev->config.rv770.sx_num_of_sets = 7;
437 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
438 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
439 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
440 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
441 rdev->config.rv770.sx_max_export_pos_size -= 16;
442 rdev->config.rv770.sx_max_export_smx_size += 16;
446 rdev->config.rv770.max_pipes = 2;
447 rdev->config.rv770.max_tile_pipes = 2;
448 rdev->config.rv770.max_simds = 2;
449 rdev->config.rv770.max_backends = 1;
450 rdev->config.rv770.max_gprs = 256;
451 rdev->config.rv770.max_threads = 192;
452 rdev->config.rv770.max_stack_entries = 256;
453 rdev->config.rv770.max_hw_contexts = 4;
454 rdev->config.rv770.max_gs_threads = 8 * 2;
455 rdev->config.rv770.sx_max_export_size = 128;
456 rdev->config.rv770.sx_max_export_pos_size = 16;
457 rdev->config.rv770.sx_max_export_smx_size = 112;
458 rdev->config.rv770.sq_num_cf_insts = 1;
460 rdev->config.rv770.sx_num_of_sets = 7;
461 rdev->config.rv770.sc_prim_fifo_size = 0x40;
462 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
463 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
466 rdev->config.rv770.max_pipes = 4;
467 rdev->config.rv770.max_tile_pipes = 4;
468 rdev->config.rv770.max_simds = 8;
469 rdev->config.rv770.max_backends = 4;
470 rdev->config.rv770.max_gprs = 256;
471 rdev->config.rv770.max_threads = 248;
472 rdev->config.rv770.max_stack_entries = 512;
473 rdev->config.rv770.max_hw_contexts = 8;
474 rdev->config.rv770.max_gs_threads = 16 * 2;
475 rdev->config.rv770.sx_max_export_size = 256;
476 rdev->config.rv770.sx_max_export_pos_size = 32;
477 rdev->config.rv770.sx_max_export_smx_size = 224;
478 rdev->config.rv770.sq_num_cf_insts = 2;
480 rdev->config.rv770.sx_num_of_sets = 7;
481 rdev->config.rv770.sc_prim_fifo_size = 0x100;
482 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
483 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
485 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
486 rdev->config.rv770.sx_max_export_pos_size -= 16;
487 rdev->config.rv770.sx_max_export_smx_size += 16;
526 if (tmp < rdev->config.rv770.max_backends) {
527 rdev->config.rv770.max_backends = tmp;
532 if (tmp < rdev->config.rv770.max_pipes) {
533 rdev->config.rv770.max_pipes = tmp;
536 if (tmp < rdev->config.rv770.max_simds) {
537 rdev->config.rv770.max_simds = tmp;
540 switch (rdev->config.rv770.max_tile_pipes) {
555 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
559 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
562 rdev->config.rv770.backend_map = tmp;
564 if (rdev->family == CHIP_RV770)
572 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
585 rdev->config.rv770.tile_config = gb_tiling_config;
618 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
621 if (rdev->family != CHIP_RV740)
627 if (rdev->family != CHIP_RV770)
632 switch (rdev->family) {
645 if (rdev->family != CHIP_RV770) {
651 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
652 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
653 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
655 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
656 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
657 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
667 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
670 switch (rdev->family) {
698 if (rdev->family == CHIP_RV710)
704 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
705 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
706 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
708 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
709 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
711 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
712 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
713 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
714 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
715 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
717 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
720 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
721 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
723 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
724 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
726 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
727 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
728 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
729 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
743 if (rdev->family == CHIP_RV710)
750 switch (rdev->family) {
763 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
809 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
815 dev_warn(rdev->dev, "limiting VRAM\n");
819 if (rdev->flags & RADEON_IS_AGP) {
824 dev_warn(rdev->dev, "limiting VRAM\n");
831 dev_warn(rdev->dev, "limiting VRAM\n");
838 dev_info(rdev->dev, "VRAM: %juM 0x%08jX - 0x%08jX (%juM used)\n",
842 radeon_vram_location(rdev, &rdev->mc, 0);
843 rdev->mc.gtt_base_align = 0;
844 radeon_gtt_location(rdev, mc);
848 static int rv770_mc_init(struct radeon_device *rdev)
854 rdev->mc.vram_is_ddr = true;
879 rdev->mc.vram_width = numchan * chansize;
881 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
882 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
884 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
885 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
886 rdev->mc.visible_vram_size = rdev->mc.aper_size;
887 r700_vram_gtt_location(rdev, &rdev->mc);
888 radeon_update_bandwidth_info(rdev);
896 * @rdev: radeon_device pointer
906 int rv770_copy_dma(struct radeon_device *rdev,
912 int ring_index = rdev->asic->copy.dma_ring_index;
913 struct radeon_ring *ring = &rdev->ring[ring_index];
918 r = radeon_semaphore_create(rdev, &sem);
926 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
929 radeon_semaphore_free(rdev, &sem, NULL);
934 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
938 radeon_semaphore_free(rdev, &sem, NULL);
955 r = radeon_fence_emit(rdev, fence, ring->idx);
957 radeon_ring_unlock_undo(rdev, ring);
961 radeon_ring_unlock_commit(rdev, ring);
962 radeon_semaphore_free(rdev, &sem, *fence);
967 static int rv770_startup(struct radeon_device *rdev)
973 rv770_pcie_gen2_enable(rdev);
975 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
976 r = r600_init_microcode(rdev);
983 r = r600_vram_scratch_init(rdev);
987 rv770_mc_program(rdev);
988 if (rdev->flags & RADEON_IS_AGP) {
989 rv770_agp_enable(rdev);
991 r = rv770_pcie_gart_enable(rdev);
996 rv770_gpu_init(rdev);
997 r = r600_blit_init(rdev);
999 r600_blit_fini(rdev);
1000 rdev->asic->copy.copy = NULL;
1001 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1005 r = radeon_wb_init(rdev);
1009 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1011 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1015 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1017 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1022 r = r600_irq_init(rdev);
1025 radeon_irq_kms_fini(rdev);
1028 r600_irq_set(rdev);
1030 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1031 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1037 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1038 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1044 r = rv770_cp_load_microcode(rdev);
1047 r = r600_cp_resume(rdev);
1051 r = r600_dma_resume(rdev);
1055 r = radeon_ib_pool_init(rdev);
1057 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1061 r = r600_audio_init(rdev);
1070 int rv770_resume(struct radeon_device *rdev)
1079 atom_asic_init(rdev->mode_info.atom_context);
1081 rdev->accel_working = true;
1082 r = rv770_startup(rdev);
1085 rdev->accel_working = false;
1093 int rv770_suspend(struct radeon_device *rdev)
1095 r600_audio_fini(rdev);
1096 r700_cp_stop(rdev);
1097 r600_dma_stop(rdev);
1098 r600_irq_suspend(rdev);
1099 radeon_wb_disable(rdev);
1100 rv770_pcie_gart_disable(rdev);
1111 int rv770_init(struct radeon_device *rdev)
1116 if (!radeon_get_bios(rdev)) {
1117 if (ASIC_IS_AVIVO(rdev))
1121 if (!rdev->is_atom_bios) {
1122 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1125 r = radeon_atombios_init(rdev);
1129 if (!radeon_card_posted(rdev)) {
1130 if (!rdev->bios) {
1131 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1135 atom_asic_init(rdev->mode_info.atom_context);
1138 r600_scratch_init(rdev);
1140 radeon_surface_init(rdev);
1142 radeon_get_clock_info(rdev->ddev);
1144 r = radeon_fence_driver_init(rdev);
1148 if (rdev->flags & RADEON_IS_AGP) {
1149 r = radeon_agp_init(rdev);
1151 radeon_agp_disable(rdev);
1153 r = rv770_mc_init(rdev);
1157 r = radeon_bo_init(rdev);
1161 r = radeon_irq_kms_init(rdev);
1165 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1166 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
1168 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
1169 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
1171 rdev->ih.ring_obj = NULL;
1172 r600_ih_ring_init(rdev, 64 * 1024);
1174 r = r600_pcie_gart_init(rdev);
1178 rdev->accel_working = true;
1179 r = rv770_startup(rdev);
1181 dev_err(rdev->dev, "disabling GPU acceleration\n");
1182 r700_cp_fini(rdev);
1183 r600_dma_fini(rdev);
1184 r600_irq_fini(rdev);
1185 radeon_wb_fini(rdev);
1186 radeon_ib_pool_fini(rdev);
1187 radeon_irq_kms_fini(rdev);
1188 rv770_pcie_gart_fini(rdev);
1189 rdev->accel_working = false;
1193 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1201 void rv770_fini(struct radeon_device *rdev)
1203 r600_blit_fini(rdev);
1204 r700_cp_fini(rdev);
1205 r600_dma_fini(rdev);
1206 r600_irq_fini(rdev);
1207 radeon_wb_fini(rdev);
1208 radeon_ib_pool_fini(rdev);
1209 radeon_irq_kms_fini(rdev);
1210 rv770_pcie_gart_fini(rdev);
1211 r600_vram_scratch_fini(rdev);
1212 radeon_gem_fini(rdev);
1213 radeon_fence_driver_fini(rdev);
1214 radeon_agp_fini(rdev);
1215 radeon_bo_fini(rdev);
1216 radeon_atombios_fini(rdev);
1217 r600_fini_microcode(rdev);
1218 free(rdev->bios, DRM_MEM_DRIVER);
1219 rdev->bios = NULL;
1222 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1232 if (rdev->flags & RADEON_IS_IGP)
1235 if (!(rdev->flags & RADEON_IS_PCIE))
1239 if (ASIC_IS_X2(rdev))
1242 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);