Lines Matching defs:tmp
52 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
56 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
57 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
81 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
82 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
132 u32 tmp;
150 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
154 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
155 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
156 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
158 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
159 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
160 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
161 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
162 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
183 u32 tmp;
196 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
197 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
198 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
199 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
200 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
201 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
202 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
203 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
217 u32 tmp;
227 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
231 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
232 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
233 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
234 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
235 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
236 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
237 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
245 u32 tmp;
259 tmp = RREG32(HDP_DEBUG1);
289 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
290 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
291 WREG32(MC_VM_FB_LOCATION, tmp);
393 u32 db_debug4, tmp;
512 for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
513 if (!(inactive_pipes & tmp)) {
516 tmp <<= 1;
525 tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16);
526 if (tmp < rdev->config.rv770.max_backends) {
527 rdev->config.rv770.max_backends = tmp;
531 tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK);
532 if (tmp < rdev->config.rv770.max_pipes) {
533 rdev->config.rv770.max_pipes = tmp;
535 tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
536 if (tmp < rdev->config.rv770.max_simds) {
537 rdev->config.rv770.max_simds = tmp;
558 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
559 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
561 gb_tiling_config |= tmp << 16;
562 rdev->config.rv770.backend_map = tmp;
850 u32 tmp;
855 tmp = RREG32(MC_ARB_RAMCFG);
856 if (tmp & CHANSIZE_OVERRIDE) {
858 } else if (tmp & CHANSIZE_MASK) {
863 tmp = RREG32(MC_SHARED_CHMAP);
864 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1224 u32 link_width_cntl, lanes, speed_cntl, tmp;
1272 tmp = RREG32(0x541c);
1273 WREG32(0x541c, tmp | 0x8);