Lines Matching defs:tmp
137 uint32_t tmp;
141 tmp = RREG32_MC(MC_STATUS);
142 if (tmp & MC_STATUS_IDLE) {
158 unsigned pipe_select_current, gb_pipe_select, tmp;
167 tmp = RREG32(R300_DST_PIPE_CONFIG);
168 pipe_select_current = (tmp >> 2) & 3;
169 tmp = (1 << pipe_select_current) |
171 WREG32_PLL(0x000D, tmp);
184 uint32_t tmp;
188 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
189 switch (tmp) {
237 uint32_t tmp;
239 tmp = RREG32(GB_PIPE_SELECT);
240 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
241 tmp = RREG32(SU_REG_DEST);
242 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
243 tmp = RREG32(GB_TILE_CONFIG);
244 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
245 tmp = RREG32(DST_PIPE_CONFIG);
246 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
255 uint32_t tmp;
257 tmp = RREG32(0x2140);
258 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
260 tmp = RREG32(0x425C);
261 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
294 u32 crtc_enabled, tmp, frame_count, blackout;
307 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
308 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
311 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
312 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
325 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
326 tmp &= ~AVIVO_CRTC_EN;
327 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
360 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
361 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
362 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
363 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
365 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
366 if (!(tmp & 1)) {
367 tmp |= 1;
368 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
376 u32 tmp, frame_count;
404 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
405 if ((tmp & 0x3) != 0) {
406 tmp &= ~0x3;
407 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
409 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
410 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
411 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
412 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
414 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
415 if (tmp & 1) {
416 tmp &= ~1;
417 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
420 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
421 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
431 tmp = RREG32(R700_MC_CITF_CNTL);
433 tmp = RREG32(R600_CITF_CNTL);
434 tmp &= ~R600_BLACKOUT_MASK;
436 WREG32(R700_MC_CITF_CNTL, tmp);
438 WREG32(R600_CITF_CNTL, tmp);
445 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
446 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
447 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
1087 u32 tmp;
1102 tmp = wm0.lb_request_fifo_depth;
1103 tmp |= wm1.lb_request_fifo_depth << 16;
1104 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1223 uint32_t tmp;
1240 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1241 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1242 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1244 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1246 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1247 WREG32_MC(MC_MISC_LAT_TIMER, tmp);