drm2/radeon/rs690.c

41 	uint32_t tmp;
45 		tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
46 		if (G_000090_MC_SYSTEM_IDLE(tmp))
74 	fixed20_12 tmp;
83 			tmp.full = dfixed_const(100);
85 			rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
90 				rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
97 			tmp.full = dfixed_const(100);
99 			rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
106 			rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
108 			rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
130 	tmp.full = dfixed_const(4);
131 	rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
135 	tmp.full = dfixed_const(5);
138 	rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
139 	if (tmp.full < rdev->pm.max_bandwidth.full) {
141 		rdev->pm.max_bandwidth.full = tmp.full;
146 	tmp.full = dfixed_const(14);
147 	rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
148 	tmp.full = dfixed_const(10);
149 	rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
178 	u32 tmp;
194 	tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
195 	tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
200 				tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
202 				tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
205 				tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
207 				tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
209 			tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
211 		tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
213 		tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
215 	WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
407 	u32 tmp;
426 		tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
427 		tmp &= C_000104_MC_DISP0R_INIT_LAT;
428 		tmp &= C_000104_MC_DISP1R_INIT_LAT;
430 			tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
432 			tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
433 		WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
445 	tmp = (wm0.lb_request_fifo_depth - 1);
446 	tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
447 	WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);