drm2/radeon/rs600.c

133 	u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
137 	tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
138 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
155 	tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
156 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
167 	u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
172 			tmp = RREG32(voltage->gpio.reg);
174 				tmp |= voltage->gpio.mask;
176 				tmp &= ~(voltage->gpio.mask);
177 			WREG32(voltage->gpio.reg, tmp);
181 			tmp = RREG32(voltage->gpio.reg);
183 				tmp &= ~voltage->gpio.mask;
185 				tmp |= voltage->gpio.mask;
186 			WREG32(voltage->gpio.reg, tmp);
261 	u32 tmp;
267 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
268 			tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
269 			WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
279 	u32 tmp;
285 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
286 			tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
287 			WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
295 	u32 tmp;
300 		tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
301 		if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
305 		tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
306 		if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
318 	u32 tmp;
323 		tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
325 			tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
327 			tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
328 		WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
331 		tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
333 			tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
335 			tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
336 		WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
397 	u32 status, tmp;
410 	tmp = RREG32(RADEON_CP_RB_CNTL);
411 	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
414 	WREG32(RADEON_CP_RB_CNTL, tmp);
461 	uint32_t tmp;
463 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
464 	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
465 	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
467 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
468 	tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
469 	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
471 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
472 	tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
473 	WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
474 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
496 	u32 tmp;
508 	tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
509 	WREG32(RADEON_BUS_CNTL, tmp);
547 	tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
548 	WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
549 	tmp = RREG32_MC(R_000009_MC_CNTL1);
550 	WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
561 	u32 tmp;
565 	tmp = RREG32_MC(R_000009_MC_CNTL1);
566 	WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
599 	uint32_t tmp = 0;
618 		tmp |= S_000040_SW_INT_EN(1);
637 	WREG32(R_000040_GEN_INT_CNTL, tmp);
650 	u32 tmp;
663 			tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
664 			tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
665 			WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
668 			tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
669 			tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
670 			WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
680 			tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
681 			tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
682 			WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);