drm2/radeon/radeon_legacy_tv.c

306 	uint32_t tmp;
315 		tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
316 		if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0)
328 	uint32_t tmp;
335 		tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
336 		if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0)
393 	uint32_t tmp;
401 		tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]);
402 		radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp);
407 		tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]);
408 		radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp);
546 	uint32_t vert_space, flicker_removal, tmp;
623 	tmp = RREG32(RADEON_TV_VSCALER_CNTL1);
624 	tmp &= 0xe3ff0000;
625 	tmp |= (vert_space * (1 << FRAC_BITS) / 10000);
626 	tv_vscaler_cntl1 = tmp;
637 	tmp = const_ptr->ver_total * 2 * 1000;
642 		tmp /= NTSC_TV_LINES_PER_FRAME;
644 		tmp /= PAL_TV_LINES_PER_FRAME;
646 	flicker_removal = (tmp + 500) / 1000;
672 	tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK;
673 	tmp = ((16384 * 256 * 10) / tmp + 5) / 10;
674 	tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
675 	tv_dac->tv.timing_cntl = tmp;
764 	tmp = RREG32(RADEON_TV_DAC_CNTL);
765 	tmp &= ~RADEON_TV_DAC_NBLANK;
766 	tmp |= RADEON_TV_DAC_BGSLEEP |
770 	WREG32(RADEON_TV_DAC_CNTL, tmp);
846 	uint32_t tmp;
855 	tmp = *h_sync_strt_wid;
856 	tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR);
857 	tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) |
859 	*h_sync_strt_wid = tmp;
864 	tmp = *v_sync_strt_wid;
865 	tmp &= ~RADEON_CRTC_V_SYNC_STRT;
866 	tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
867 	*v_sync_strt_wid = tmp;