Lines Matching defs:tmp
411 u32 tmp, reg;
426 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
427 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
554 tmp = RREG32(i2c_cntl_0);
555 if (tmp & RADEON_I2C_GO)
557 tmp = RREG32(i2c_cntl_0);
558 if (tmp & RADEON_I2C_DONE)
561 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
562 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
586 tmp = RREG32(i2c_cntl_0);
587 if (tmp & RADEON_I2C_GO)
589 tmp = RREG32(i2c_cntl_0);
590 if (tmp & RADEON_I2C_DONE)
593 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
594 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
614 tmp = RREG32(i2c_cntl_0);
615 if (tmp & RADEON_I2C_GO)
617 tmp = RREG32(i2c_cntl_0);
618 if (tmp & RADEON_I2C_DONE)
621 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
622 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
640 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
641 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
642 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
662 u32 tmp, reg;
672 tmp = RREG32(rec->mask_clk_reg);
673 tmp &= ~rec->mask_clk_mask;
674 WREG32(rec->mask_clk_reg, tmp);
675 tmp = RREG32(rec->mask_clk_reg);
677 tmp = RREG32(rec->mask_data_reg);
678 tmp &= ~rec->mask_data_mask;
679 WREG32(rec->mask_data_reg, tmp);
680 tmp = RREG32(rec->mask_data_reg);
683 tmp = RREG32(rec->a_clk_reg);
684 tmp &= ~rec->a_clk_mask;
685 WREG32(rec->a_clk_reg, tmp);
686 tmp = RREG32(rec->a_clk_reg);
688 tmp = RREG32(rec->a_data_reg);
689 tmp &= ~rec->a_data_mask;
690 WREG32(rec->a_data_reg, tmp);
691 tmp = RREG32(rec->a_data_reg);
694 tmp = RREG32(rec->en_clk_reg);
695 tmp &= ~rec->en_clk_mask;
696 WREG32(rec->en_clk_reg, tmp);
697 tmp = RREG32(rec->en_clk_reg);
699 tmp = RREG32(rec->en_data_reg);
700 tmp &= ~rec->en_data_mask;
701 WREG32(rec->en_data_reg, tmp);
702 tmp = RREG32(rec->en_data_reg);
705 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
706 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
761 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
762 if (tmp & AVIVO_DC_I2C_GO)
764 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
765 if (tmp & AVIVO_DC_I2C_DONE)
768 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
803 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
804 if (tmp & AVIVO_DC_I2C_GO)
806 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
807 if (tmp & AVIVO_DC_I2C_DONE)
810 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
846 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
847 if (tmp & AVIVO_DC_I2C_GO)
849 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
850 if (tmp & AVIVO_DC_I2C_DONE)
853 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
876 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
877 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
878 WREG32(RADEON_BIOS_6_SCRATCH, tmp);