drm2/radeon/r600_blit_kms.c

43 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
57 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
58 	radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
59 	radeon_ring_write(ring, gpu_addr >> 8);
62 		radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
63 		radeon_ring_write(ring, 2 << 0);
66 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
67 	radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
68 	radeon_ring_write(ring, (pitch << 0) | (slice << 10));
70 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
71 	radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
72 	radeon_ring_write(ring, 0);
74 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
75 	radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
76 	radeon_ring_write(ring, cb_color_info);
78 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
79 	radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
80 	radeon_ring_write(ring, 0);
82 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
83 	radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
84 	radeon_ring_write(ring, 0);
86 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
87 	radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
88 	radeon_ring_write(ring, 0);
97 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
105 	radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
106 	radeon_ring_write(ring, sync_type);
107 	radeon_ring_write(ring, cp_coher_size);
108 	radeon_ring_write(ring, mc_addr >> 8);
109 	radeon_ring_write(ring, 10); /* poll interval */
116 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
125 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
126 	radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
127 	radeon_ring_write(ring, gpu_addr >> 8);
129 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
130 	radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
131 	radeon_ring_write(ring, sq_pgm_resources);
133 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
134 	radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
135 	radeon_ring_write(ring, 0);
139 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
140 	radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
141 	radeon_ring_write(ring, gpu_addr >> 8);
143 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
144 	radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
145 	radeon_ring_write(ring, sq_pgm_resources | (1 << 28));
147 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
148 	radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
149 	radeon_ring_write(ring, 2);
151 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
152 	radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
153 	radeon_ring_write(ring, 0);
163 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
172 	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
173 	radeon_ring_write(ring, 0x460);
174 	radeon_ring_write(ring, gpu_addr & 0xffffffff);
175 	radeon_ring_write(ring, 48 - 1);
176 	radeon_ring_write(ring, sq_vtx_constant_word2);
177 	radeon_ring_write(ring, 1 << 0);
178 	radeon_ring_write(ring, 0);
179 	radeon_ring_write(ring, 0);
180 	radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30);
200 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
223 	radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
224 	radeon_ring_write(ring, 0);
225 	radeon_ring_write(ring, sq_tex_resource_word0);
226 	radeon_ring_write(ring, sq_tex_resource_word1);
227 	radeon_ring_write(ring, gpu_addr >> 8);
228 	radeon_ring_write(ring, gpu_addr >> 8);
229 	radeon_ring_write(ring, sq_tex_resource_word4);
230 	radeon_ring_write(ring, 0);
231 	radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30);
239 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
240 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
241 	radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
242 	radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
243 	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
245 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
246 	radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
247 	radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
248 	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
250 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
251 	radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
252 	radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1U << 31));
253 	radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
260 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
261 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
262 	radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
263 	radeon_ring_write(ring, DI_PT_RECTLIST);
265 	radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
266 	radeon_ring_write(ring,
272 	radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
273 	radeon_ring_write(ring, 1);
275 	radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
276 	radeon_ring_write(ring, 3);
277 	radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
285 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
441 	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
442 	radeon_ring_write(ring,
447 	radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
448 	radeon_ring_write(ring, dwords);
451 	radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6));
452 	radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
453 	radeon_ring_write(ring, sq_config);
454 	radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
455 	radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
456 	radeon_ring_write(ring, sq_thread_resource_mgmt);
457 	radeon_ring_write(ring, sq_stack_resource_mgmt_1);
458 	radeon_ring_write(ring, sq_stack_resource_mgmt_2);
636 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
666 	r = radeon_ring_lock(rdev, ring, ring_size);
674 		radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring,
689 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
694 		radeon_ring_unlock_undo(rdev, ring);
698 	radeon_ring_unlock_commit(rdev, ring);