drm2/radeon/r300.c

61 	uint32_t tmp;
66 		tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
67 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
69 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
119 	uint32_t tmp;
131 	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
132 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
134 	tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
135 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
145 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
146 	tmp |= RADEON_PCIE_TX_GART_EN;
147 	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
148 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
159 	u32 tmp;
165 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
166 	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
167 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
315 	uint32_t tmp;
319 		tmp = RREG32(RADEON_MC_STATUS);
320 		if (tmp & R300_MC_IDLE) {
330 	uint32_t gb_tile_config, tmp;
364 	tmp = RREG32(R300_DST_PIPE_CONFIG);
365 	WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
386 	u32 status, tmp;
398 	tmp = RREG32(RADEON_CP_RB_CNTL);
399 	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
402 	WREG32(RADEON_CP_RB_CNTL, tmp);
446 	u32 tmp;
450 	tmp = RREG32(RADEON_MEM_CNTL);
451 	tmp &= R300_MEM_NUM_CHANNELS_MASK;
452 	switch (tmp) {
565 	uint32_t tmp;
567 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
568 	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
569 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
570 	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
571 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
572 	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
573 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
574 	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
575 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
576 	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
577 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
578 	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
579 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
580 	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
605 	uint32_t tmp, tile_flags = 0;
697 			tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
698 			tmp |= tile_flags;
699 			ib[idx] = tmp;
766 			tmp = idx_value & ~(0x7 << 16);
767 			tmp |= tile_flags;
768 			ib[idx] = tmp;
851 			tmp = idx_value & ~(0x7 << 16);
852 			tmp |= tile_flags;
853 			ib[idx] = tmp;
886 		tmp = (idx_value >> 25) & 0x3;
887 		track->textures[i].tex_coord_type = tmp;
972 		tmp = idx_value & 0x7;
973 		if (tmp == 2 || tmp == 4 || tmp == 6) {
976 		tmp = (idx_value >> 3) & 0x7;
977 		if (tmp == 2 || tmp == 4 || tmp == 6) {
1000 		tmp = idx_value & 0x3FFF;
1001 		track->textures[i].pitch = tmp + 1;
1003 			tmp = ((idx_value >> 15) & 1) << 11;
1004 			track->textures[i].width_11 = tmp;
1005 			tmp = ((idx_value >> 16) & 1) << 11;
1006 			track->textures[i].height_11 = tmp;
1038 		tmp = idx_value & 0x7FF;
1039 		track->textures[i].width = tmp + 1;
1040 		tmp = (idx_value >> 11) & 0x7FF;
1041 		track->textures[i].height = tmp + 1;
1042 		tmp = (idx_value >> 26) & 0xF;
1043 		track->textures[i].num_levels = tmp;
1044 		tmp = idx_value & (1U << 31);
1045 		track->textures[i].use_pitch = !!tmp;
1046 		tmp = (idx_value >> 22) & 0xF;
1047 		track->textures[i].txdepth = tmp;
1341 	u32 tmp;
1346 	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1347 	tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1349 		tmp |= S_00000D_FORCE_VAP(1);
1350 	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);