Lines Matching refs:rdev
72 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
87 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
107 * @rdev: radeon_device pointer
112 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
116 if (crtc >= rdev->num_crtc)
130 while (r100_is_in_vblank(rdev, crtc)) {
132 if (!r100_is_counter_moving(rdev, crtc))
137 while (!r100_is_in_vblank(rdev, crtc)) {
139 if (!r100_is_counter_moving(rdev, crtc))
148 * @rdev: radeon_device pointer
154 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
157 radeon_irq_kms_pflip_irq_get(rdev, crtc);
163 * @rdev: radeon_device pointer
169 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
172 radeon_irq_kms_pflip_irq_put(rdev, crtc);
178 * @rdev: radeon_device pointer
188 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
190 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
199 for (i = 0; i < rdev->usec_timeout; i++) {
217 * @rdev: radeon_device pointer
223 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
226 rdev->pm.dynpm_can_upclock = true;
227 rdev->pm.dynpm_can_downclock = true;
229 switch (rdev->pm.dynpm_planned_action) {
231 rdev->pm.requested_power_state_index = 0;
232 rdev->pm.dynpm_can_downclock = false;
235 if (rdev->pm.current_power_state_index == 0) {
236 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
237 rdev->pm.dynpm_can_downclock = false;
239 if (rdev->pm.active_crtc_count > 1) {
240 for (i = 0; i < rdev->pm.num_power_states; i++) {
241 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
243 else if (i >= rdev->pm.current_power_state_index) {
244 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
247 rdev->pm.requested_power_state_index = i;
252 rdev->pm.requested_power_state_index =
253 rdev->pm.current_power_state_index - 1;
256 if ((rdev->pm.active_crtc_count > 0) &&
257 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
259 rdev->pm.requested_power_state_index++;
263 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
264 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
265 rdev->pm.dynpm_can_upclock = false;
267 if (rdev->pm.active_crtc_count > 1) {
268 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
269 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
271 else if (i <= rdev->pm.current_power_state_index) {
272 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
275 rdev->pm.requested_power_state_index = i;
280 rdev->pm.requested_power_state_index =
281 rdev->pm.current_power_state_index + 1;
285 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
286 rdev->pm.dynpm_can_upclock = false;
294 rdev->pm.requested_clock_mode_index = 0;
297 rdev->pm.power_state[rdev->pm.requested_power_state_index].
298 clock_info[rdev->pm.requested_clock_mode_index].sclk,
299 rdev->pm.power_state[rdev->pm.requested_power_state_index].
300 clock_info[rdev->pm.requested_clock_mode_index].mclk,
301 rdev->pm.power_state[rdev->pm.requested_power_state_index].
308 * @rdev: radeon_device pointer
314 void r100_pm_init_profile(struct radeon_device *rdev)
317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
356 * @rdev: radeon_device pointer
361 void r100_pm_misc(struct radeon_device *rdev)
363 int requested_index = rdev->pm.requested_power_state_index;
364 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
441 if ((rdev->flags & RADEON_IS_PCIE) &&
442 !(rdev->flags & RADEON_IS_IGP) &&
443 rdev->asic->pm.set_pcie_lanes &&
445 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
446 radeon_set_pcie_lanes(rdev,
455 * @rdev: radeon_device pointer
459 void r100_pm_prepare(struct radeon_device *rdev)
461 struct drm_device *ddev = rdev->ddev;
486 * @rdev: radeon_device pointer
490 void r100_pm_finish(struct radeon_device *rdev)
492 struct drm_device *ddev = rdev->ddev;
517 * @rdev: radeon_device pointer
522 bool r100_gui_idle(struct radeon_device *rdev)
534 * @rdev: radeon_device pointer
540 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
562 * @rdev: radeon_device pointer
567 void r100_hpd_set_polarity(struct radeon_device *rdev,
571 bool connected = r100_hpd_sense(rdev, hpd);
598 * @rdev: radeon_device pointer
603 void r100_hpd_init(struct radeon_device *rdev)
605 struct drm_device *dev = rdev->ddev;
612 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
614 radeon_irq_kms_enable_hpd(rdev, enable);
620 * @rdev: radeon_device pointer
625 void r100_hpd_fini(struct radeon_device *rdev)
627 struct drm_device *dev = rdev->ddev;
635 radeon_irq_kms_disable_hpd(rdev, disable);
641 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
649 int r100_pci_gart_init(struct radeon_device *rdev)
653 if (rdev->gart.ptr) {
658 r = radeon_gart_init(rdev);
661 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
662 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
663 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
664 return radeon_gart_table_ram_alloc(rdev);
667 int r100_pci_gart_enable(struct radeon_device *rdev)
671 radeon_gart_restore(rdev);
676 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
677 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
679 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
682 r100_pci_gart_tlb_flush(rdev);
684 (unsigned)(rdev->mc.gtt_size >> 20),
685 (unsigned long long)rdev->gart.table_addr);
686 rdev->gart.ready = true;
690 void r100_pci_gart_disable(struct radeon_device *rdev)
701 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
703 u32 *gtt = rdev->gart.ptr;
705 if (i < 0 || i > rdev->gart.num_gpu_pages) {
712 void r100_pci_gart_fini(struct radeon_device *rdev)
714 radeon_gart_fini(rdev);
715 r100_pci_gart_disable(rdev);
716 radeon_gart_table_ram_free(rdev);
719 int r100_irq_set(struct radeon_device *rdev)
723 if (!rdev->irq.installed) {
728 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
731 if (rdev->irq.crtc_vblank_int[0] ||
732 atomic_read(&rdev->irq.pflip[0])) {
735 if (rdev->irq.crtc_vblank_int[1] ||
736 atomic_read(&rdev->irq.pflip[1])) {
739 if (rdev->irq.hpd[0]) {
742 if (rdev->irq.hpd[1]) {
749 void r100_irq_disable(struct radeon_device *rdev)
760 static uint32_t r100_irq_ack(struct radeon_device *rdev)
773 irqreturn_t r100_irq_process(struct radeon_device *rdev)
778 status = r100_irq_ack(rdev);
782 if (rdev->shutdown) {
788 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
792 if (rdev->irq.crtc_vblank_int[0]) {
793 drm_handle_vblank(rdev->ddev, 0);
794 rdev->pm.vblank_sync = true;
795 DRM_WAKEUP(&rdev->irq.vblank_queue);
797 if (atomic_read(&rdev->irq.pflip[0]))
798 radeon_crtc_handle_flip(rdev, 0);
801 if (rdev->irq.crtc_vblank_int[1]) {
802 drm_handle_vblank(rdev->ddev, 1);
803 rdev->pm.vblank_sync = true;
804 DRM_WAKEUP(&rdev->irq.vblank_queue);
806 if (atomic_read(&rdev->irq.pflip[1]))
807 radeon_crtc_handle_flip(rdev, 1);
817 status = r100_irq_ack(rdev);
820 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work);
821 if (rdev->msi_enabled) {
822 switch (rdev->family) {
837 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
847 void r100_fence_ring_emit(struct radeon_device *rdev,
850 struct radeon_ring *ring = &rdev->ring[fence->ring];
862 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
865 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
867 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
873 void r100_semaphore_ring_emit(struct radeon_device *rdev,
882 int r100_copy_blit(struct radeon_device *rdev,
888 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
906 r = radeon_ring_lock(rdev, ring, ndw);
950 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
952 radeon_ring_unlock_commit(rdev, ring);
956 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
961 for (i = 0; i < rdev->usec_timeout; i++) {
971 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
975 r = radeon_ring_lock(rdev, ring, 2);
985 radeon_ring_unlock_commit(rdev, ring);
990 static int r100_cp_init_microcode(struct radeon_device *rdev)
997 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
998 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
999 (rdev->family == CHIP_RS200)) {
1002 } else if ((rdev->family == CHIP_R200) ||
1003 (rdev->family == CHIP_RV250) ||
1004 (rdev->family == CHIP_RV280) ||
1005 (rdev->family == CHIP_RS300)) {
1008 } else if ((rdev->family == CHIP_R300) ||
1009 (rdev->family == CHIP_R350) ||
1010 (rdev->family == CHIP_RV350) ||
1011 (rdev->family == CHIP_RV380) ||
1012 (rdev->family == CHIP_RS400) ||
1013 (rdev->family == CHIP_RS480)) {
1016 } else if ((rdev->family == CHIP_R420) ||
1017 (rdev->family == CHIP_R423) ||
1018 (rdev->family == CHIP_RV410)) {
1021 } else if ((rdev->family == CHIP_RS690) ||
1022 (rdev->family == CHIP_RS740)) {
1025 } else if (rdev->family == CHIP_RS600) {
1028 } else if ((rdev->family == CHIP_RV515) ||
1029 (rdev->family == CHIP_R520) ||
1030 (rdev->family == CHIP_RV530) ||
1031 (rdev->family == CHIP_R580) ||
1032 (rdev->family == CHIP_RV560) ||
1033 (rdev->family == CHIP_RV570)) {
1039 rdev->me_fw = firmware_get(fw_name);
1040 if (rdev->me_fw == NULL) {
1044 } else if (rdev->me_fw->datasize % 8) {
1047 rdev->me_fw->datasize, fw_name);
1049 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD);
1050 rdev->me_fw = NULL;
1058 * @rdev: radeon_device pointer
1063 static void r100_cp_fini_microcode (struct radeon_device *rdev)
1066 if (rdev->me_fw != NULL) {
1067 firmware_put(rdev->me_fw, FIRMWARE_UNLOAD);
1068 rdev->me_fw = NULL;
1072 static void r100_cp_load_microcode(struct radeon_device *rdev)
1077 if (r100_gui_wait_for_idle(rdev)) {
1082 if (rdev->me_fw) {
1083 size = rdev->me_fw->datasize / 4;
1084 fw_data = (const __be32 *)rdev->me_fw->data;
1095 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1097 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1108 if (r100_debugfs_cp_init(rdev)) {
1111 if (!rdev->me_fw) {
1112 r = r100_cp_init_microcode(rdev);
1122 r100_cp_load_microcode(rdev);
1123 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1174 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1175 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1177 if (rdev->wb.enabled)
1196 pci_enable_busmaster(rdev->dev);
1198 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1199 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1205 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1208 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1209 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1218 void r100_cp_fini(struct radeon_device *rdev)
1220 if (r100_cp_wait_for_idle(rdev)) {
1224 r100_cp_disable(rdev);
1225 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1226 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1230 void r100_cp_disable(struct radeon_device *rdev)
1233 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1234 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1238 if (r100_gui_wait_for_idle(rdev)) {
1515 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
2060 r = r100_cs_track_check(p->rdev, track);
2072 r = r100_cs_track_check(p->rdev, track);
2084 r = r100_cs_track_check(p->rdev, track);
2091 r = r100_cs_track_check(p->rdev, track);
2098 r = r100_cs_track_check(p->rdev, track);
2105 r = r100_cs_track_check(p->rdev, track);
2112 r = r100_cs_track_check(p->rdev, track);
2119 if (p->rdev->hyperz_filp != p->filp)
2140 r100_cs_track_clear(p->rdev, track);
2152 if (p->rdev->family >= CHIP_R200)
2154 p->rdev->config.r100.reg_safe_bm,
2155 p->rdev->config.r100.reg_safe_bm_size,
2159 p->rdev->config.r100.reg_safe_bm,
2160 p->rdev->config.r100.reg_safe_bm_size,
2233 static int r100_cs_track_cube(struct radeon_device *rdev,
2264 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2285 if (rdev->family < CHIP_R300)
2291 if (rdev->family >= CHIP_RV515)
2298 if (rdev->family >= CHIP_RV515)
2325 ret = r100_cs_track_cube(rdev, track, u);
2346 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2432 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2451 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2478 return r100_cs_track_texture_check(rdev, track);
2483 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2492 if (rdev->family < CHIP_R300) {
2494 if (rdev->family <= CHIP_RS200)
2536 if (rdev->family <= CHIP_RS200) {
2563 static void r100_errata(struct radeon_device *rdev)
2565 rdev->pll_errata = 0;
2567 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2568 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2571 if (rdev->family == CHIP_RV100 ||
2572 rdev->family == CHIP_RS100 ||
2573 rdev->family == CHIP_RS200) {
2574 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2578 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2583 for (i = 0; i < rdev->usec_timeout; i++) {
2593 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2598 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2602 for (i = 0; i < rdev->usec_timeout; i++) {
2612 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2617 for (i = 0; i < rdev->usec_timeout; i++) {
2628 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2638 radeon_ring_force_activity(rdev, ring);
2639 return radeon_ring_test_lockup(rdev, ring);
2643 void r100_enable_bm(struct radeon_device *rdev)
2651 void r100_bm_disable(struct radeon_device *rdev)
2664 pci_disable_busmaster(rdev->dev);
2668 int r100_asic_reset(struct radeon_device *rdev)
2678 r100_mc_stop(rdev, &save);
2680 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2689 pci_save_state(device_get_parent(rdev->dev));
2691 r100_bm_disable(rdev);
2701 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2709 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2711 pci_restore_state(device_get_parent(rdev->dev));
2712 r100_enable_bm(rdev);
2716 dev_err(rdev->dev, "failed to reset GPU\n");
2719 dev_info(rdev->dev, "GPU reset succeed\n");
2720 r100_mc_resume(rdev, &save);
2724 void r100_set_common_regs(struct radeon_device *rdev)
2726 struct drm_device *dev = rdev->ddev;
2811 static void r100_vram_get_type(struct radeon_device *rdev)
2815 rdev->mc.vram_is_ddr = false;
2816 if (rdev->flags & RADEON_IS_IGP)
2817 rdev->mc.vram_is_ddr = true;
2819 rdev->mc.vram_is_ddr = true;
2820 if ((rdev->family == CHIP_RV100) ||
2821 (rdev->family == CHIP_RS100) ||
2822 (rdev->family == CHIP_RS200)) {
2825 rdev->mc.vram_width = 32;
2827 rdev->mc.vram_width = 64;
2829 if (rdev->flags & RADEON_SINGLE_CRTC) {
2830 rdev->mc.vram_width /= 4;
2831 rdev->mc.vram_is_ddr = true;
2833 } else if (rdev->family <= CHIP_RV280) {
2836 rdev->mc.vram_width = 128;
2838 rdev->mc.vram_width = 64;
2842 rdev->mc.vram_width = 128;
2846 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2856 if (rdev->family == CHIP_RV280 ||
2857 rdev->family >= CHIP_RV350) {
2868 byte = pci_read_config(rdev->dev, 0xe, 1);
2884 void r100_vram_init_sizes(struct radeon_device *rdev)
2889 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
2890 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2891 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2893 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2894 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2896 if (rdev->flags & RADEON_IS_IGP) {
2900 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2901 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2902 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2904 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2908 if (rdev->mc.real_vram_size == 0) {
2909 rdev->mc.real_vram_size = 8192 * 1024;
2910 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2915 if (rdev->mc.aper_size > config_aper_size)
2916 config_aper_size = rdev->mc.aper_size;
2918 if (config_aper_size > rdev->mc.real_vram_size)
2919 rdev->mc.mc_vram_size = config_aper_size;
2921 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2925 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2939 static void r100_mc_init(struct radeon_device *rdev)
2943 r100_vram_get_type(rdev);
2944 r100_vram_init_sizes(rdev);
2945 base = rdev->mc.aper_base;
2946 if (rdev->flags & RADEON_IS_IGP)
2948 radeon_vram_location(rdev, &rdev->mc, base);
2949 rdev->mc.gtt_base_align = 0;
2950 if (!(rdev->flags & RADEON_IS_AGP))
2951 radeon_gtt_location(rdev, &rdev->mc);
2952 radeon_update_bandwidth_info(rdev);
2959 void r100_pll_errata_after_index(struct radeon_device *rdev)
2961 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2967 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2972 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2981 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2992 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2997 r100_pll_errata_after_index(rdev);
2999 r100_pll_errata_after_data(rdev);
3003 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
3006 r100_pll_errata_after_index(rdev);
3008 r100_pll_errata_after_data(rdev);
3011 static void r100_set_safe_registers(struct radeon_device *rdev)
3013 if (ASIC_IS_RN50(rdev)) {
3014 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
3015 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
3016 } else if (rdev->family < CHIP_R200) {
3017 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
3018 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
3020 r200_set_safe_registers(rdev);
3032 struct radeon_device *rdev = dev->dev_private;
3053 struct radeon_device *rdev = dev->dev_private;
3054 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3058 radeon_ring_free_size(rdev, ring);
3079 struct radeon_device *rdev = dev->dev_private;
3129 struct radeon_device *rdev = dev->dev_private;
3169 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3172 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3178 int r100_debugfs_cp_init(struct radeon_device *rdev)
3181 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3187 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3190 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3196 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3203 if (rdev->family <= CHIP_RS200) {
3209 } else if (rdev->family <= CHIP_RV280) {
3229 if (ASIC_IS_RN50(rdev))
3234 if (rdev->family < CHIP_R300)
3247 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3253 void r100_bandwidth_update(struct radeon_device *rdev)
3324 radeon_update_display_priority(rdev);
3326 if (rdev->mode_info.crtcs[0]->base.enabled) {
3327 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3328 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3330 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3331 if (rdev->mode_info.crtcs[1]->base.enabled) {
3332 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3333 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3339 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3354 sclk_ff = rdev->pm.sclk;
3355 mclk_ff = rdev->pm.mclk;
3357 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3387 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3391 } else if (rdev->family == CHIP_R300 ||
3392 rdev->family == CHIP_R350) { /* r300, r350 */
3396 } else if (rdev->family == CHIP_RV350 ||
3397 rdev->family <= CHIP_RV380) {
3402 } else if (rdev->family == CHIP_R420 ||
3403 rdev->family == CHIP_R423 ||
3404 rdev->family == CHIP_RV410) {
3428 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3429 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3436 if (rdev->family == CHIP_RS400 ||
3437 rdev->family == CHIP_RS480) {
3444 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3465 if (rdev->family == CHIP_RV410 ||
3466 rdev->family == CHIP_R420 ||
3467 rdev->family == CHIP_R423)
3476 if (rdev->flags & RADEON_IS_AGP) {
3484 if (ASIC_IS_R300(rdev)) {
3487 if ((rdev->family == CHIP_RV100) ||
3488 rdev->flags & RADEON_IS_IGP) {
3489 if (rdev->mc.vram_is_ddr)
3494 if (rdev->mc.vram_width == 128)
3503 if (rdev->mc.vram_is_ddr) {
3504 if (rdev->mc.vram_width == 32) {
3531 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3553 if (ASIC_IS_RV100(rdev))
3582 if (rdev->disp_priority == 2) {
3593 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3602 if ((rdev->family == CHIP_R350) &&
3618 if ((rdev->family == CHIP_RS400) ||
3619 (rdev->family == CHIP_RS480)) {
3658 if ((rdev->family == CHIP_R350) &&
3668 if ((rdev->family == CHIP_RS100) ||
3669 (rdev->family == CHIP_RS200))
3672 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3692 if (rdev->disp_priority == 2) {
3701 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3709 if ((rdev->family == CHIP_RS400) ||
3710 (rdev->family == CHIP_RS480)) {
3737 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3744 r = radeon_scratch_get(rdev, &scratch);
3750 r = radeon_ring_lock(rdev, ring, 2);
3753 radeon_scratch_free(rdev, scratch);
3758 radeon_ring_unlock_commit(rdev, ring);
3759 for (i = 0; i < rdev->usec_timeout; i++) {
3766 if (i < rdev->usec_timeout) {
3773 radeon_scratch_free(rdev, scratch);
3777 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3779 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3792 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3800 r = radeon_scratch_get(rdev, &scratch);
3806 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3820 r = radeon_ib_schedule(rdev, &ib, NULL);
3830 for (i = 0; i < rdev->usec_timeout; i++) {
3837 if (i < rdev->usec_timeout) {
3845 radeon_ib_free(rdev, &ib);
3847 radeon_scratch_free(rdev, scratch);
3851 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3856 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3864 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3881 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3893 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3896 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3897 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3898 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3904 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3909 void r100_vga_render_disable(struct radeon_device *rdev)
3917 static void r100_debugfs(struct radeon_device *rdev)
3921 r = r100_debugfs_mc_info_init(rdev);
3923 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3926 static void r100_mc_program(struct radeon_device *rdev)
3931 r100_mc_stop(rdev, &save);
3932 if (rdev->flags & RADEON_IS_AGP) {
3934 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3935 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3936 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3937 if (rdev->family > CHIP_RV200)
3939 upper_32_bits(rdev->mc.agp_base) & 0xff);
3943 if (rdev->family > CHIP_RV200)
3947 if (r100_mc_wait_for_idle(rdev))
3948 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3951 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3952 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3953 r100_mc_resume(rdev, &save);
3956 static void r100_clock_startup(struct radeon_device *rdev)
3961 radeon_legacy_set_clock_gating(rdev, 1);
3965 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3970 static int r100_startup(struct radeon_device *rdev)
3975 r100_set_common_regs(rdev);
3977 r100_mc_program(rdev);
3979 r100_clock_startup(rdev);
3982 r100_enable_bm(rdev);
3983 if (rdev->flags & RADEON_IS_PCI) {
3984 r = r100_pci_gart_enable(rdev);
3990 r = radeon_wb_init(rdev);
3994 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3996 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4001 r100_irq_set(rdev);
4002 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
4004 r = r100_cp_init(rdev, 1024 * 1024);
4006 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
4010 r = radeon_ib_pool_init(rdev);
4012 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4019 int r100_resume(struct radeon_device *rdev)
4024 if (rdev->flags & RADEON_IS_PCI)
4025 r100_pci_gart_disable(rdev);
4027 r100_clock_startup(rdev);
4029 if (radeon_asic_reset(rdev)) {
4030 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4035 radeon_combios_asic_init(rdev->ddev);
4037 r100_clock_startup(rdev);
4039 radeon_surface_init(rdev);
4041 rdev->accel_working = true;
4042 r = r100_startup(rdev);
4044 rdev->accel_working = false;
4049 int r100_suspend(struct radeon_device *rdev)
4051 r100_cp_disable(rdev);
4052 radeon_wb_disable(rdev);
4053 r100_irq_disable(rdev);
4054 if (rdev->flags & RADEON_IS_PCI)
4055 r100_pci_gart_disable(rdev);
4059 void r100_fini(struct radeon_device *rdev)
4061 r100_cp_fini(rdev);
4062 radeon_wb_fini(rdev);
4063 radeon_ib_pool_fini(rdev);
4064 radeon_gem_fini(rdev);
4065 if (rdev->flags & RADEON_IS_PCI)
4066 r100_pci_gart_fini(rdev);
4067 radeon_agp_fini(rdev);
4068 radeon_irq_kms_fini(rdev);
4069 radeon_fence_driver_fini(rdev);
4070 radeon_bo_fini(rdev);
4071 radeon_atombios_fini(rdev);
4072 r100_cp_fini_microcode(rdev);
4073 free(rdev->bios, DRM_MEM_DRIVER);
4074 rdev->bios = NULL;
4084 void r100_restore_sanity(struct radeon_device *rdev)
4102 int r100_init(struct radeon_device *rdev)
4107 r100_debugfs(rdev);
4109 r100_vga_render_disable(rdev);
4111 radeon_scratch_init(rdev);
4113 radeon_surface_init(rdev);
4115 r100_restore_sanity(rdev);
4118 if (!radeon_get_bios(rdev)) {
4119 if (ASIC_IS_AVIVO(rdev))
4122 if (rdev->is_atom_bios) {
4123 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4126 r = radeon_combios_init(rdev);
4131 if (radeon_asic_reset(rdev)) {
4132 dev_warn(rdev->dev,
4138 if (radeon_boot_test_post_card(rdev) == false)
4141 r100_errata(rdev);
4143 radeon_get_clock_info(rdev->ddev);
4145 if (rdev->flags & RADEON_IS_AGP) {
4146 r = radeon_agp_init(rdev);
4148 radeon_agp_disable(rdev);
4152 r100_mc_init(rdev);
4154 r = radeon_fence_driver_init(rdev);
4157 r = radeon_irq_kms_init(rdev);
4161 r = radeon_bo_init(rdev);
4164 if (rdev->flags & RADEON_IS_PCI) {
4165 r = r100_pci_gart_init(rdev);
4169 r100_set_safe_registers(rdev);
4171 rdev->accel_working = true;
4172 r = r100_startup(rdev);
4175 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4176 r100_cp_fini(rdev);
4177 radeon_wb_fini(rdev);
4178 radeon_ib_pool_fini(rdev);
4179 radeon_irq_kms_fini(rdev);
4180 if (rdev->flags & RADEON_IS_PCI)
4181 r100_pci_gart_fini(rdev);
4182 rdev->accel_working = false;
4187 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
4190 if (reg < rdev->rmmio_size && !always_indirect)
4191 return bus_read_4(rdev->rmmio, reg);
4196 DRM_SPINLOCK_IRQSAVE(&rdev->mmio_idx_lock, flags);
4197 bus_write_4(rdev->rmmio, RADEON_MM_INDEX, reg);
4198 ret = bus_read_4(rdev->rmmio, RADEON_MM_DATA);
4199 DRM_SPINUNLOCK_IRQRESTORE(&rdev->mmio_idx_lock, flags);
4205 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
4208 if (reg < rdev->rmmio_size && !always_indirect)
4209 bus_write_4(rdev->rmmio, reg, v);
4213 DRM_SPINLOCK_IRQSAVE(&rdev->mmio_idx_lock, flags);
4214 bus_write_4(rdev->rmmio, RADEON_MM_INDEX, reg);
4215 bus_write_4(rdev->rmmio, RADEON_MM_DATA, v);
4216 DRM_SPINUNLOCK_IRQRESTORE(&rdev->mmio_idx_lock, flags);
4220 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4222 if (reg < rdev->rio_mem_size)
4223 return bus_read_4(rdev->rio_mem, reg);
4226 bus_write_4(rdev->rio_mem, RADEON_MM_INDEX, reg);
4227 return bus_read_4(rdev->rio_mem, RADEON_MM_DATA);
4231 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4233 if (reg < rdev->rio_mem_size)
4234 bus_write_4(rdev->rio_mem, reg, v);
4237 bus_write_4(rdev->rio_mem, RADEON_MM_INDEX, reg);
4238 bus_write_4(rdev->rio_mem, RADEON_MM_DATA, v);