Lines Matching +full:barts_pfp +full:. +full:bin
2 * Copyright 2010 Advanced Micro Devices, Inc.
12 * all copies or substantial portions of the Software.
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD: releng/11.0/sys/dev/drm2/radeon/ni.c 280183 2015-03-17 18:50:33Z dumbbell $");
28 #include <dev/drm2/drmP.h>
29 #include "radeon.h"
30 #include "radeon_asic.h"
31 #include <dev/drm2/radeon/radeon_drm.h>
32 #include "nid.h"
33 #include "atom.h"
34 #include "ni_reg.h"
35 #include "cayman_blit_shaders.h"
37 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
47 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
66 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
67 MODULE_FIRMWARE("radeon/BARTS_me.bin");
68 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
69 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
70 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
71 MODULE_FIRMWARE("radeon/TURKS_me.bin");
72 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
73 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
74 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
75 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
76 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
77 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
78 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
79 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
80 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
81 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
82 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
435 * Drop the pfp, me, mc and rlc firmwares image references.
436 * Called at driver shutdown.
481 rdev->config.cayman.max_shader_engines = 2;
482 rdev->config.cayman.max_pipes_per_simd = 4;
483 rdev->config.cayman.max_tile_pipes = 8;
484 rdev->config.cayman.max_simds_per_se = 12;
485 rdev->config.cayman.max_backends_per_se = 4;
486 rdev->config.cayman.max_texture_channel_caches = 8;
487 rdev->config.cayman.max_gprs = 256;
488 rdev->config.cayman.max_threads = 256;
489 rdev->config.cayman.max_gs_threads = 32;
490 rdev->config.cayman.max_stack_entries = 512;
491 rdev->config.cayman.sx_num_of_sets = 8;
492 rdev->config.cayman.sx_max_export_size = 256;
493 rdev->config.cayman.sx_max_export_pos_size = 64;
494 rdev->config.cayman.sx_max_export_smx_size = 192;
495 rdev->config.cayman.max_hw_contexts = 8;
496 rdev->config.cayman.sq_num_cf_insts = 2;
498 rdev->config.cayman.sc_prim_fifo_size = 0x100;
499 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
500 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
505 rdev->config.cayman.max_shader_engines = 1;
506 rdev->config.cayman.max_pipes_per_simd = 4;
507 rdev->config.cayman.max_tile_pipes = 2;
522 rdev->config.cayman.max_simds_per_se = 6;
523 rdev->config.cayman.max_backends_per_se = 2;
532 rdev->config.cayman.max_simds_per_se = 4;
533 rdev->config.cayman.max_backends_per_se = 2;
542 rdev->config.cayman.max_simds_per_se = 3;
543 rdev->config.cayman.max_backends_per_se = 1;
545 rdev->config.cayman.max_simds_per_se = 2;
546 rdev->config.cayman.max_backends_per_se = 1;
548 rdev->config.cayman.max_texture_channel_caches = 2;
549 rdev->config.cayman.max_gprs = 256;
550 rdev->config.cayman.max_threads = 256;
551 rdev->config.cayman.max_gs_threads = 32;
552 rdev->config.cayman.max_stack_entries = 512;
553 rdev->config.cayman.sx_num_of_sets = 8;
554 rdev->config.cayman.sx_max_export_size = 256;
555 rdev->config.cayman.sx_max_export_pos_size = 64;
556 rdev->config.cayman.sx_max_export_smx_size = 192;
557 rdev->config.cayman.max_hw_contexts = 8;
558 rdev->config.cayman.sq_num_cf_insts = 2;
560 rdev->config.cayman.sc_prim_fifo_size = 0x40;
561 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
562 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
584 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
585 if (rdev->config.cayman.mem_row_size_in_kb > 4)
586 rdev->config.cayman.mem_row_size_in_kb = 4;
588 rdev->config.cayman.shader_engine_tile_size = 32;
589 rdev->config.cayman.num_gpus = 1;
590 rdev->config.cayman.multi_gpu_tile_size = 64;
593 rdev->config.cayman.num_tile_pipes = (1 << tmp);
595 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
597 rdev->config.cayman.num_shader_engines = tmp + 1;
599 rdev->config.cayman.num_gpus = tmp + 1;
601 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
603 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
606 /* setup tiling info dword. gb_addr_config is not adequate since it does
607 * not have bank info, so create a custom tiling dword.
613 rdev->config.cayman.tile_config = 0;
614 switch (rdev->config.cayman.num_tile_pipes) {
617 rdev->config.cayman.tile_config |= (0 << 0);
620 rdev->config.cayman.tile_config |= (1 << 0);
623 rdev->config.cayman.tile_config |= (2 << 0);
626 rdev->config.cayman.tile_config |= (3 << 0);
630 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
632 rdev->config.cayman.tile_config |= 1 << 4;
636 rdev->config.cayman.tile_config |= 0 << 4;
639 rdev->config.cayman.tile_config |= 1 << 4;
643 rdev->config.cayman.tile_config |= 2 << 4;
647 rdev->config.cayman.tile_config |=
649 rdev->config.cayman.tile_config |=
653 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
676 if ((rdev->config.cayman.max_backends_per_se == 1) &&
688 rdev->config.cayman.max_backends_per_se *
689 rdev->config.cayman.max_shader_engines,
695 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
717 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
733 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
734 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
735 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
737 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
738 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
739 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
746 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
805 if (rdev->gart.robj == NULL) {
806 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
831 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
832 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
833 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
835 (u32)(rdev->dummy_page.addr >> 12));
847 * on the fly in the vm part of radeon_gart.c
851 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
853 rdev->gart.table_addr >> 12);
858 (u32)(rdev->dummy_page.addr >> 12));
875 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
876 (unsigned)(rdev->mc.gtt_size >> 20),
877 (unsigned long long)rdev->gart.table_addr);
878 rdev->gart.ready = true;
919 * CP.
925 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
987 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
990 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1028 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1034 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1044 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1146 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1163 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1189 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1190 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1191 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1195 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1196 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1197 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1207 * DMA engine. The programming model is very similar
1208 * to the 3D engine (ring buffer, IBs, etc.), but the
1210 * different form the PM4 format used by the 3D engine.
1212 * solid fills, and a number of other things. It also
1213 * has support for tiling/detiling of buffers.
1214 * Cayman and newer support two asynchronous DMA engines.
1222 * Schedule an IB in the DMA ring (cayman-SI).
1229 if (rdev->wb.enabled) {
1240 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
1241 * Pad as necessary with NOPs.
1256 * Stop the async dma engines (cayman-SI).
1262 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1274 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
1275 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
1283 * Set up the DMA ring buffers and enable them. (cayman-SI).
1284 * Returns 0 for success, error for failure.
1328 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
1330 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
1332 if (rdev->wb.enabled)
1364 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1374 * Stop the async dma engines and free the rings (cayman-SI).
1537 * Check if the async DMA engine is locked up (cayman-SI).
1538 * Returns true if the engine appears to be locked up, false if not.
1602 rdev->asic->copy.copy = NULL;
1622 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1628 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1634 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1640 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1646 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1653 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1694 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1700 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
1717 * shape.
1720 atom_asic_init(rdev->mode_info.atom_context);
1746 * do nothing more than calling asic specific function. This
1748 * like vram_info.
1775 DRM_INFO("GPU not posted. posting now...\n");
1776 atom_asic_init(rdev->mode_info.atom_context);
1812 rdev->ih.ring_obj = NULL;
1836 /* Don't start up if the MC ucode is missing.
1838 * is loaded are not suffient for advanced operations.
1841 * ucode.
1844 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1880 rdev->vm_manager.nvm = 8;
1885 rdev->vm_manager.vram_base_offset = tmp;
1887 rdev->vm_manager.vram_base_offset = 0;
1924 * Update the page tables using the CP (cayman-si).
1930 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
1935 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
1993 * using the CP (cayman-si).