Lines Matching defs:tmp
475 u32 tmp;
583 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
584 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
592 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
593 rdev->config.cayman.num_tile_pipes = (1 << tmp);
594 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
595 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
596 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
597 rdev->config.cayman.num_shader_engines = tmp + 1;
598 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
599 rdev->config.cayman.num_gpus = tmp + 1;
600 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
601 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
602 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
603 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
652 tmp = 0;
659 tmp <<= 4;
660 tmp |= rb_disable_bitmap;
663 disabled_rb_mask = tmp;
680 tmp = 0x11111111;
683 tmp = 0x00000000;
686 tmp = gb_addr_config & NUM_PIPES_MASK;
687 tmp = r6xx_remap_render_backend(rdev, tmp,
692 WREG32(GB_BACKEND_MAP, tmp);
777 tmp = RREG32(HDP_MISC_CNTL);
778 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
779 WREG32(HDP_MISC_CNTL, tmp);
1453 u32 tmp;
1462 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1463 tmp &= ~DMA_RB_ENABLE;
1464 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1467 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1468 tmp &= ~DMA_RB_ENABLE;
1469 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1883 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1884 tmp <<= 22;
1885 rdev->vm_manager.vram_base_offset = tmp;