Lines Matching refs:args
94 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
111 args.ucAction = ATOM_LCD_BLOFF;
112 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
116 args.ucAction = ATOM_LCD_BLON;
117 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
360 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
364 memset(&args, 0, sizeof(args));
377 args.ucAction = action;
380 args.ucDacStandard = ATOM_DAC1_PS2;
382 args.ucDacStandard = ATOM_DAC1_CV;
390 args.ucDacStandard = ATOM_DAC1_PAL;
396 args.ucDacStandard = ATOM_DAC1_NTSC;
400 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
402 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
412 TV_ENCODER_CONTROL_PS_ALLOCATION args;
416 memset(&args, 0, sizeof(args));
420 args.sTVEncoder.ucAction = action;
423 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
427 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
430 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
433 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
436 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
439 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
442 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
445 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
448 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
451 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
456 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
458 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
500 union dvo_encoder_control args;
504 memset(&args, 0, sizeof(args));
518 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
521 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
523 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
527 args.dvo.sDVOEncoder.ucAction = action;
528 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
530 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
533 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
537 args.dvo_v3.ucAction = action;
538 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
539 args.dvo_v3.ucDVOConfig = 0; /* XXX */
551 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
566 union lvds_encoder_control args;
577 memset(&args, 0, sizeof(args));
603 args.v1.ucMisc = 0;
604 args.v1.ucAction = action;
606 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
607 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
610 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
612 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
615 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
617 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
619 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
624 args.v2.ucMisc = 0;
625 args.v2.ucAction = action;
628 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
631 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
632 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
633 args.v2.ucTruncate = 0;
634 args.v2.ucSpatial = 0;
635 args.v2.ucTemporal = 0;
636 args.v2.ucFRC = 0;
639 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
641 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
643 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
646 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
648 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
650 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
654 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
656 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
669 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
809 union dig_encoder_control args;
830 memset(&args, 0, sizeof(args));
848 args.v1.ucAction = action;
849 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
851 args.v3.ucPanelMode = panel_mode;
853 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
855 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
856 args.v1.ucLaneNum = dp_lane_count;
858 args.v1.ucLaneNum = 8;
860 args.v1.ucLaneNum = 4;
862 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
863 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
866 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
870 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
873 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
877 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
879 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
883 args.v3.ucAction = action;
884 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
886 args.v3.ucPanelMode = panel_mode;
888 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
890 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
891 args.v3.ucLaneNum = dp_lane_count;
893 args.v3.ucLaneNum = 8;
895 args.v3.ucLaneNum = 4;
897 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
898 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
899 args.v3.acConfig.ucDigSel = dig->dig_encoder;
900 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
903 args.v4.ucAction = action;
904 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
906 args.v4.ucPanelMode = panel_mode;
908 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
910 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
911 args.v4.ucLaneNum = dp_lane_count;
913 args.v4.ucLaneNum = 8;
915 args.v4.ucLaneNum = 4;
917 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
919 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
921 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
923 args.v4.acConfig.ucDigSel = dig->dig_encoder;
924 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
926 args.v4.ucHPD_ID = 0;
928 args.v4.ucHPD_ID = hpd_id + 1;
940 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
960 union dig_transmitter_control args;
1006 memset(&args, 0, sizeof(args));
1029 args.v1.ucAction = action;
1031 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1033 args.v1.asMode.ucLaneSel = lane_num;
1034 args.v1.asMode.ucLaneSet = lane_set;
1037 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1039 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1041 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1044 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1047 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1049 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1056 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1058 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1060 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1062 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1065 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1067 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1072 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1074 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1077 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1080 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1082 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1086 args.v2.ucAction = action;
1088 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1090 args.v2.asMode.ucLaneSel = lane_num;
1091 args.v2.asMode.ucLaneSet = lane_set;
1094 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1096 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1098 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1101 args.v2.acConfig.ucEncoderSel = dig_encoder;
1103 args.v2.acConfig.ucLinkSel = 1;
1107 args.v2.acConfig.ucTransmitterSel = 0;
1110 args.v2.acConfig.ucTransmitterSel = 1;
1113 args.v2.acConfig.ucTransmitterSel = 2;
1118 args.v2.acConfig.fCoherentMode = 1;
1119 args.v2.acConfig.fDPConnector = 1;
1122 args.v2.acConfig.fCoherentMode = 1;
1124 args.v2.acConfig.fDualLinkConnector = 1;
1128 args.v3.ucAction = action;
1130 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1132 args.v3.asMode.ucLaneSel = lane_num;
1133 args.v3.asMode.ucLaneSet = lane_set;
1136 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1138 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1140 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1144 args.v3.ucLaneNum = dp_lane_count;
1146 args.v3.ucLaneNum = 8;
1148 args.v3.ucLaneNum = 4;
1151 args.v3.acConfig.ucLinkSel = 1;
1153 args.v3.acConfig.ucEncoderSel = 1;
1161 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1163 args.v3.acConfig.ucRefClkSource = pll_id;
1167 args.v3.acConfig.ucTransmitterSel = 0;
1170 args.v3.acConfig.ucTransmitterSel = 1;
1173 args.v3.acConfig.ucTransmitterSel = 2;
1178 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1181 args.v3.acConfig.fCoherentMode = 1;
1183 args.v3.acConfig.fDualLinkConnector = 1;
1187 args.v4.ucAction = action;
1189 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1191 args.v4.asMode.ucLaneSel = lane_num;
1192 args.v4.asMode.ucLaneSet = lane_set;
1195 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1197 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1199 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1203 args.v4.ucLaneNum = dp_lane_count;
1205 args.v4.ucLaneNum = 8;
1207 args.v4.ucLaneNum = 4;
1210 args.v4.acConfig.ucLinkSel = 1;
1212 args.v4.acConfig.ucEncoderSel = 1;
1221 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1223 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1225 args.v4.acConfig.ucRefClkSource = pll_id;
1229 args.v4.acConfig.ucTransmitterSel = 0;
1232 args.v4.acConfig.ucTransmitterSel = 1;
1235 args.v4.acConfig.ucTransmitterSel = 2;
1240 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1243 args.v4.acConfig.fCoherentMode = 1;
1245 args.v4.acConfig.fDualLinkConnector = 1;
1249 args.v5.ucAction = action;
1251 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1253 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1258 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1260 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1264 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1266 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1270 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1272 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1276 args.v5.ucLaneNum = dp_lane_count;
1278 args.v5.ucLaneNum = 8;
1280 args.v5.ucLaneNum = 4;
1281 args.v5.ucConnObjId = connector_object_id;
1282 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1285 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1287 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1290 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1293 args.v5.asConfig.ucCoherentMode = 1;
1296 args.v5.asConfig.ucHPDSel = 0;
1298 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1299 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1300 args.v5.ucDPLaneSet = lane_set;
1312 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1321 union dig_transmitter_control args;
1338 memset(&args, 0, sizeof(args));
1340 args.v1.ucAction = action;
1342 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1373 union external_encoder_control args;
1398 memset(&args, 0, sizeof(args));
1411 args.v1.sDigEncoder.ucAction = action;
1412 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1413 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1415 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1417 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1418 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1420 args.v1.sDigEncoder.ucLaneNum = 8;
1422 args.v1.sDigEncoder.ucLaneNum = 4;
1425 args.v3.sExtEncoder.ucAction = action;
1427 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1429 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1430 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1432 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1434 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1436 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1437 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1439 args.v3.sExtEncoder.ucLaneNum = 8;
1441 args.v3.sExtEncoder.ucLaneNum = 4;
1444 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1447 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1450 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1453 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1464 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1474 ENABLE_YUV_PS_ALLOCATION args;
1478 memset(&args, 0, sizeof(args));
1496 args.ucEnable = ATOM_ENABLE;
1497 args.ucCRTC = radeon_crtc->crtc_id;
1499 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1510 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1513 memset(&args, 0, sizeof(args));
1558 args.ucAction = ATOM_ENABLE;
1563 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1566 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1568 args.ucAction = ATOM_LCD_BLON;
1569 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1575 args.ucAction = ATOM_DISABLE;
1576 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1578 args.ucAction = ATOM_LCD_BLOFF;
1579 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1797 union crtc_source_param args;
1802 memset(&args, 0, sizeof(args));
1813 args.v1.ucCRTC = radeon_crtc->crtc_id;
1816 args.v1.ucCRTC = radeon_crtc->crtc_id;
1818 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1824 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1829 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1831 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1836 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1841 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1843 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1845 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1850 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1852 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1854 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1859 args.v2.ucCRTC = radeon_crtc->crtc_id;
1864 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1866 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1868 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1870 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1879 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1882 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1885 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1888 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1891 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1894 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1899 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1903 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1905 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1907 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1911 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1913 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1915 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1926 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2179 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2183 memset(&args, 0, sizeof(args));
2188 args.sDacload.ucMisc = 0;
2192 args.sDacload.ucDacType = ATOM_DAC_A;
2194 args.sDacload.ucDacType = ATOM_DAC_B;
2197 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2199 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2201 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2203 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2205 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2207 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2210 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);