drm2/i915/intel_display.c

1015 		int reg = PIPECONF(cpu_transcoder);
1226 	reg = PIPECONF(cpu_transcoder);
1686 	pipeconf_val = I915_READ(PIPECONF(pipe));
1730 	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1834 	reg = PIPECONF(cpu_transcoder);
1873 	reg = PIPECONF(cpu_transcoder);
2824 	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2898 	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2925 	/* BPC in FDI rx is consistent with that in PIPECONF */
2927 	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
3160 		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
4780 	pipeconf = I915_READ(PIPECONF(pipe));
4852 	I915_WRITE(PIPECONF(pipe), pipeconf);
4853 	POSTING_READ(PIPECONF(pipe));
5197 	val = I915_READ(PIPECONF(pipe));
5228 	I915_WRITE(PIPECONF(pipe), val);
5229 	POSTING_READ(PIPECONF(pipe));
5241 	val = I915_READ(PIPECONF(cpu_transcoder));
5253 	I915_WRITE(PIPECONF(cpu_transcoder), val);
5254 	POSTING_READ(PIPECONF(cpu_transcoder));
5820 	WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
9103 	reg = PIPECONF(crtc->cpu_transcoder);
9277 		tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9510 		error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));