dev/drm/i915_drv.h

138 	u32 irq_mask_reg;
139 	u32 pipestat[2];
151 	u32 saveDSPACNTR;
152 	u32 saveDSPBCNTR;
153 	u32 saveDSPARB;
154 	u32 saveRENDERSTANDBY;
155 	u32 saveHWS;
156 	u32 savePIPEACONF;
157 	u32 savePIPEBCONF;
158 	u32 savePIPEASRC;
159 	u32 savePIPEBSRC;
160 	u32 saveFPA0;
161 	u32 saveFPA1;
162 	u32 saveDPLL_A;
163 	u32 saveDPLL_A_MD;
164 	u32 saveHTOTAL_A;
165 	u32 saveHBLANK_A;
166 	u32 saveHSYNC_A;
167 	u32 saveVTOTAL_A;
168 	u32 saveVBLANK_A;
169 	u32 saveVSYNC_A;
170 	u32 saveBCLRPAT_A;
171 	u32 savePIPEASTAT;
172 	u32 saveDSPASTRIDE;
173 	u32 saveDSPASIZE;
174 	u32 saveDSPAPOS;
175 	u32 saveDSPAADDR;
176 	u32 saveDSPASURF;
177 	u32 saveDSPATILEOFF;
178 	u32 savePFIT_PGM_RATIOS;
179 	u32 saveBLC_PWM_CTL;
180 	u32 saveBLC_PWM_CTL2;
181 	u32 saveFPB0;
182 	u32 saveFPB1;
183 	u32 saveDPLL_B;
184 	u32 saveDPLL_B_MD;
185 	u32 saveHTOTAL_B;
186 	u32 saveHBLANK_B;
187 	u32 saveHSYNC_B;
188 	u32 saveVTOTAL_B;
189 	u32 saveVBLANK_B;
190 	u32 saveVSYNC_B;
191 	u32 saveBCLRPAT_B;
192 	u32 savePIPEBSTAT;
193 	u32 saveDSPBSTRIDE;
194 	u32 saveDSPBSIZE;
195 	u32 saveDSPBPOS;
196 	u32 saveDSPBADDR;
197 	u32 saveDSPBSURF;
198 	u32 saveDSPBTILEOFF;
199 	u32 saveVGA0;
200 	u32 saveVGA1;
201 	u32 saveVGA_PD;
202 	u32 saveVGACNTRL;
203 	u32 saveADPA;
204 	u32 saveLVDS;
205 	u32 savePP_ON_DELAYS;
206 	u32 savePP_OFF_DELAYS;
207 	u32 saveDVOA;
208 	u32 saveDVOB;
209 	u32 saveDVOC;
210 	u32 savePP_ON;
211 	u32 savePP_OFF;
212 	u32 savePP_CONTROL;
213 	u32 savePP_DIVISOR;
214 	u32 savePFIT_CONTROL;
215 	u32 save_palette_a[256];
216 	u32 save_palette_b[256];
217 	u32 saveFBC_CFB_BASE;
218 	u32 saveFBC_LL_BASE;
219 	u32 saveFBC_CONTROL;
220 	u32 saveFBC_CONTROL2;
221 	u32 saveIER;
222 	u32 saveIIR;
223 	u32 saveIMR;
224 	u32 saveCACHE_MODE_0;
225 	u32 saveD_STATE;
226 	u32 saveCG_2D_DIS;
227 	u32 saveMI_ARB_STATE;
228 	u32 saveSWF0[16];
229 	u32 saveSWF1[16];
230 	u32 saveSWF2[3];
454 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
455 extern u32 g45_get_vblank_counter(struct drm_device *dev, int crtc);
460 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
463 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
620 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])