Lines Matching refs:DELAY
311 DELAY(50);
329 DELAY(10);
350 DELAY(10);
356 DELAY(10);
361 DELAY(10);
366 DELAY(10);
924 DELAY(10);
1597 DELAY(1000000);
1643 DELAY(1000000);
1690 DELAY(10); /* Wait 10 microseconds (actually 50 PCI cycles but at
1699 DELAY(200000);
1710 DELAY(1000);
1801 DELAY(200000);
1814 DELAY(1000);
1864 #define EMIT do { TULIP_CSR_WRITE(sc, csr_srom_mii, csr); DELAY(1); } while (0)
1934 #define MII_EMIT do { TULIP_CSR_WRITE(sc, csr_srom_mii, csr); DELAY(1); } while (0)
2287 DELAY(100);
2298 DELAY(10000);
2533 DELAY(10);
2538 DELAY(10);
2550 DELAY(10000);
2636 DELAY(10);
2642 DELAY(10);
2651 DELAY(10000);
3166 DELAY(10); /* Wait 10 microseconds (actually 50 PCI cycles but at
4727 DELAY(10); /* Wait 10 microseconds (actually 50 PCI cycles but at
4813 DELAY(11*1000);
4859 DELAY(100); /* Wait 10 microseconds (actually 50 PCI cycles but at