dev/cadence/if_cgem.c

195 #define WR4(sc, off, val) 	(bus_write_4((sc)->mem_res, (off), (val)))
259 	WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |
261 	WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);
264 		WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0);
265 		WR4(sc, CGEM_SPEC_ADDR_HI(i), 0);
350 	WR4(sc, CGEM_HASH_TOP, hash_hi);
351 	WR4(sc, CGEM_HASH_BOT, hash_lo);
352 	WR4(sc, CGEM_NET_CFG, net_cfg);
809 		WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow |
916 		WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow &
919 		WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
944 	WR4(sc, CGEM_INTR_STAT, istatus);
957 		WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_HRESP_NOT_OK);
963 		WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_OVERRUN);
969 		WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow |
989 	WR4(sc, CGEM_NET_CTRL, 0);
990 	WR4(sc, CGEM_NET_CFG, 0);
991 	WR4(sc, CGEM_NET_CTRL, CGEM_NET_CTRL_CLR_STAT_REGS);
992 	WR4(sc, CGEM_TX_STAT, CGEM_TX_STAT_ALL);
993 	WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_ALL);
994 	WR4(sc, CGEM_INTR_DIS, CGEM_INTR_ALL);
995 	WR4(sc, CGEM_HASH_BOT, 0);
996 	WR4(sc, CGEM_HASH_TOP, 0);
997 	WR4(sc, CGEM_TX_QBAR, 0);	/* manual says do this. */
998 	WR4(sc, CGEM_RX_QBAR, 0);
1001 	WR4(sc, CGEM_NET_CFG,
1006 	WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
1034 	WR4(sc, CGEM_NET_CFG, net_cfg);
1047 	WR4(sc, CGEM_DMA_CFG, dma_cfg);
1050 	WR4(sc, CGEM_RX_QBAR, (uint32_t) sc->rxring_physaddr);
1051 	WR4(sc, CGEM_TX_QBAR, (uint32_t) sc->txring_physaddr);
1055 	WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
1058 	WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |
1060 	WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);
1063 	WR4(sc, CGEM_INTR_EN,
1217 				WR4(sc, CGEM_DMA_CFG,
1226 				WR4(sc, CGEM_DMA_CFG,
1236 				WR4(sc, CGEM_NET_CFG,
1243 				WR4(sc, CGEM_NET_CFG,
1315 	WR4(sc, CGEM_PHY_MAINT,
1349 	WR4(sc, CGEM_PHY_MAINT,
1440 	WR4(sc, CGEM_NET_CFG, net_cfg);