Lines Matching refs:x7
2258 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
2274 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
2275 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
2286 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
2823 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2828 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2833 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2838 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2843 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
3093 #define MDIO_PMA_REG_10G_CTRL2 0x7
3206 #define MDIO_AN_DEVAD 0x7
3336 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
3607 #define IGU_FID_PF_NUM_MASK (0x7)
3631 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))