dev/bxe/bxe_elink.c

2765 	uint32_t wb_data[2];
2776 	wb_data[0] = val;
2777 	wb_data[1] = 0;
2778 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
2786 	wb_data[0] = val;
2787 	wb_data[1] = 0;
2788 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2798 	uint32_t wb_data[2];
2809 	wb_data[0] = val;
2810 	wb_data[1] = 0;
2811 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2820 	wb_data[0] = val;
2821 	wb_data[1] = 0;
2822 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2827 		wb_data[0] = 0x0;
2828 		wb_data[0] |= (1<<0);  /* RX */
2829 		wb_data[0] |= (1<<1);  /* TX */
2830 		wb_data[0] |= (1<<2);  /* Force initial Xon */
2831 		wb_data[0] |= (1<<3);  /* 8 cos */
2832 		wb_data[0] |= (1<<5);  /* STATS */
2833 		wb_data[1] = 0;
2835 			    wb_data, 2);
2837 		wb_data[0] &= ~(1<<2);
2841 		wb_data[0] = 0x8;
2842 		wb_data[1] = 0;
2845 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2856 	wb_data[0] = val;
2857 	wb_data[1] = 0;
2859 		    wb_data, 2);
2871 	wb_data[0] = val;
2872 	wb_data[1] = 0;
2873 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
3091 	uint32_t wb_data[2];
3097 	wb_data[0] = 0x3c;
3098 	wb_data[1] = 0;
3100 		    wb_data, 2);
3103 	wb_data[0] = ((params->mac_addr[2] << 24) |
3107 	wb_data[1] = ((params->mac_addr[0] << 8) |
3109 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
3117 	wb_data[0] = val;
3118 	wb_data[1] = 0;
3119 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
3122 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3123 	wb_data[1] = 0;
3124 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
3129 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3130 	wb_data[1] = 0;
3131 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
3134 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3135 	wb_data[1] = 0;
3136 	REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3139 	wb_data[0] = 0x1000200;
3140 	wb_data[1] = 0;
3142 		    wb_data, 2);
3146 		wb_data[0] = 0xf000;
3147 		wb_data[1] = 0;
3149 			    wb_data, 2);
3164 	uint32_t wb_data[2];
3168 	wb_data[0] = 0;
3169 	wb_data[1] = 0;
3170 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
3174 	wb_data[0] = 0x3c;
3175 	wb_data[1] = 0;
3177 		    wb_data, 2);
3182 	wb_data[0] = ((params->mac_addr[2] << 24) |
3186 	wb_data[1] = ((params->mac_addr[0] << 8) |
3189 		    wb_data, 2);
3194 	wb_data[0] = 0x1000200;
3195 	wb_data[1] = 0;
3197 		    wb_data, 2);
3201 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3202 	wb_data[1] = 0;
3203 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
3207 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3208 	wb_data[1] = 0;
3209 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
3212 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
3213 	wb_data[1] = 0;
3214 	REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3270 	uint32_t wb_data[2];
3282 		REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
3284 			wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
3286 			wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
3287 		REG_WR_DMAE(sc, bmac_addr, wb_data, 2);
14753 		uint32_t wb_data[2];
14762 		REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);
14763 		lss_status = (wb_data[0] > 0);