Lines Matching refs:CSR_WRITE_4
977 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
979 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
1149 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1173 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1175 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1185 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1187 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1569 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1572 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
2361 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2365 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2382 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2387 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2389 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2712 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2730 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2749 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2808 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2825 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
3281 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3305 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3487 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3571 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3608 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3617 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3636 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3644 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3649 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3656 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3665 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);