Lines Matching refs:CSR_WRITE_2
217 CSR_WRITE_2(sc, data_reg, v);
230 CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16);
234 CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff);
278 CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
349 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
366 CSR_WRITE_2(sc, 0x60e, 0);
367 CSR_WRITE_2(sc, 0x610, 0x8000);
368 CSR_WRITE_2(sc, 0x604, 0);
369 CSR_WRITE_2(sc, 0x606, 0x200);
393 CSR_WRITE_2(sc, BWI_MAC_POWERUP_DELAY, sc->sc_pwron_delay);
442 CSR_WRITE_2(sc, 0x612, 0x50); /* Force Pre-TBTT to 80? */
477 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
720 CSR_WRITE_2(sc, 0x568, 0);
721 CSR_WRITE_2(sc, 0x7c0, 0);
722 CSR_WRITE_2(sc, 0x50c, val_50c);
723 CSR_WRITE_2(sc, 0x508, 0);
724 CSR_WRITE_2(sc, 0x50a, 0);
725 CSR_WRITE_2(sc, 0x54c, 0);
726 CSR_WRITE_2(sc, 0x56a, 0x14);
727 CSR_WRITE_2(sc, 0x568, 0x826);
728 CSR_WRITE_2(sc, 0x500, 0);
729 CSR_WRITE_2(sc, 0x502, 0x30);
1200 CSR_WRITE_2(sc, ofs, val16);
1301 CSR_WRITE_2(sc, BWI_MAC_PRE_TBTT, pre_tbtt);
1547 CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
1619 CSR_WRITE_2(mac->mac_sc, BWI_MAC_SLOTTIME,