Lines Matching refs:POW_SM
958 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
962 POW_SM(ratesArray[rate18mb], 24)
963 | POW_SM(ratesArray[rate12mb], 16)
964 | POW_SM(ratesArray[rate9mb], 8)
965 | POW_SM(ratesArray[rate6mb], 0)
968 POW_SM(ratesArray[rate54mb], 24)
969 | POW_SM(ratesArray[rate48mb], 16)
970 | POW_SM(ratesArray[rate36mb], 8)
971 | POW_SM(ratesArray[rate24mb], 0)
977 POW_SM(ratesArray[rate2s], 24)
978 | POW_SM(ratesArray[rate2l], 16)
979 | POW_SM(ratesArray[rateXr], 8) /* XR target power */
980 | POW_SM(ratesArray[rate1l], 0)
983 POW_SM(ratesArray[rate11s], 24)
984 | POW_SM(ratesArray[rate11l], 16)
985 | POW_SM(ratesArray[rate5_5s], 8)
986 | POW_SM(ratesArray[rate5_5l], 0)
996 POW_SM(ratesArray[rateHt20_3], 24)
997 | POW_SM(ratesArray[rateHt20_2], 16)
998 | POW_SM(ratesArray[rateHt20_1], 8)
999 | POW_SM(ratesArray[rateHt20_0], 0)
1002 POW_SM(ratesArray[rateHt20_7], 24)
1003 | POW_SM(ratesArray[rateHt20_6], 16)
1004 | POW_SM(ratesArray[rateHt20_5], 8)
1005 | POW_SM(ratesArray[rateHt20_4], 0)
1011 POW_SM(ratesArray[rateHt40_3], 24)
1012 | POW_SM(ratesArray[rateHt40_2], 16)
1013 | POW_SM(ratesArray[rateHt40_1], 8)
1014 | POW_SM(ratesArray[rateHt40_0], 0)
1017 POW_SM(ratesArray[rateHt40_7], 24)
1018 | POW_SM(ratesArray[rateHt40_6], 16)
1019 | POW_SM(ratesArray[rateHt40_5], 8)
1020 | POW_SM(ratesArray[rateHt40_4], 0)
1024 POW_SM(ratesArray[rateExtOfdm], 24)
1025 | POW_SM(ratesArray[rateExtCck], 16)
1026 | POW_SM(ratesArray[rateDupOfdm], 8)
1027 | POW_SM(ratesArray[rateDupCck], 0)
1037 #undef POW_SM
1052 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
1221 POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1222 | POW_SM(pModal->pwrDecreaseFor2Chain, 0)
1225 #undef POW_SM