dev/ale/if_ale.c

210 	CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
236 	CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
293 		CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
367 		CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
375 		CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
1503 		CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1506 		CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1525 	CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1533 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1539 		CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1934 		CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
2105 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2236 	CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT);
2260 	CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
2303 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2598 	CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2600 	CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2660 	CSR_WRITE_4(sc, ALE_PAR0,
2662 	CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2668 	CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2674 	CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2675 	CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2676 	CSR_WRITE_4(sc, ALE_TPD_CNT,
2680 	CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2682 	CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2685 	CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2687 	CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2689 	CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2699 	CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2701 	CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2704 	CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2711 	CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2718 	CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2726 	CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2736 	CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2738 	CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2744 	CSR_WRITE_4(sc, ALE_HDPX_CFG,
2762 		CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2771 	CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2776 		CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2784 		CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2792 	CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2793 	CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2796 	CSR_WRITE_4(sc, ALE_RXQ_CFG,
2803 	CSR_WRITE_4(sc, ALE_DMA_CFG,
2818 	CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2840 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2847 	CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2848 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2849 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2880 	CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2881 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2885 	CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2888 	CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2891 	CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2896 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2925 		CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
3004 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
3029 		CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
3030 		CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
3031 		CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3048 	CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
3049 	CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
3050 	CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);