dev/age/if_age.c

218 	CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
247 	CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
347 		CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
355 		CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
389 	CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
391 	CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
1332 		CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1425 	CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs);
1433 		CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1888 			CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1962 	CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2006 		CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
2009 		CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2126 	CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2167 	CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2205 	CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2541 	CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
2553 	CSR_WRITE_4(sc, 0x12FC, 0x6500);
2554 	CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2611 	CSR_WRITE_4(sc, AGE_PAR0,
2613 	CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
2617 	CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
2619 	CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
2621 	CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
2623 	CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
2625 	CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
2627 	CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
2629 	CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
2634 	CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
2638 	CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
2654 	CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
2661 	CSR_WRITE_4(sc, AGE_HDPX_CFG,
2679 	CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
2692 	CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
2695 	CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
2709 		CSR_WRITE_4(sc, 0x12FC, 0x6500);
2714 		CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2750 	CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
2755 	CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
2762 	CSR_WRITE_4(sc, AGE_RXQ_CFG,
2772 	CSR_WRITE_4(sc, AGE_TXQ_CFG,
2781 	CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG,
2787 	CSR_WRITE_4(sc, AGE_DMA_CFG,
2793 	CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
2800 	CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
2804 	CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
2805 	CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
2811 	CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
2820 	CSR_WRITE_4(sc, AGE_MAC_CFG,
2834 	CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2835 	CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
2838 	CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2872 	CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
2873 	CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
2875 	CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
2880 	CSR_WRITE_4(sc, AGE_DMA_CFG,
2883 	CSR_WRITE_4(sc, AGE_TXQ_CFG,
2885 	CSR_WRITE_4(sc, AGE_RXQ_CFG,
2938 		CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2944 		CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2967 		CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2973 		CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
3141 	CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
3166 		CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF);
3167 		CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF);
3168 		CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3185 	CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
3186 	CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
3187 	CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);