contrib/octeon-sdk/cvmx-helper-xaui.c

88 int __cvmx_helper_xaui_enumerate(int interface)
93 	gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
102  * Probe a XAUI interface and determine the number of ports
103  * connected to it. The XAUI interface should still be down
106  * @param interface Interface to probe
108  * @return Number of ports on the interface. Zero to disable.
110 int __cvmx_helper_xaui_probe(int interface)
152         qlm = cvmx_qlm_interface(interface);
158     /* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the interface
161     mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
163     cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
165     __cvmx_helper_setup_gmx(interface, 1);
170 	    all of the PKO packet ports for this interface to the XAUI. This allows
181 	    pko_mem_port_ptrs.s.eid = interface*4;
182 	    pko_mem_port_ptrs.s.pid = interface*16 + i;
187     return __cvmx_helper_xaui_enumerate(interface);
192  * Bringup XAUI interface. After this call packet I/O should be
195  * @param interface Interface to bring up
199 static int __cvmx_helper_xaui_link_init(int interface)
209     xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
211     cvmx_write_csr (CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
214     cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0,interface), 0x0);
215     cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
216     cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
221     gmxXauiTxCtl.u64 = cvmx_read_csr (CVMX_GMXX_TX_XAUI_CTL(interface));
224     cvmx_write_csr (CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
227     xauiCtl.u64 = cvmx_read_csr (CVMX_PCSXX_CONTROL1_REG(interface));
237     cvmx_write_csr (CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
240     if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_CONTROL1_REG(interface), cvmx_pcsxx_control1_reg_t, reset, ==, 0, 10000))
243     if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_10GBX_STATUS_REG(interface), cvmx_pcsxx_10gbx_status_reg_t, alignd, ==, 1, 10000))
246     if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_RX_XAUI_CTL(interface), cvmx_gmxx_rx_xaui_ctl_t, status, ==, 0, 10000))
252     if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(0, interface), cvmx_gmxx_prtx_cfg_t, rx_idle, ==, 1, 10000))
255     if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(0, interface), cvmx_gmxx_prtx_cfg_t, tx_idle, ==, 1, 10000))
259     gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
263     cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
264     cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
265     cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
266     cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
269     if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS1_REG(interface), cvmx_pcsxx_status1_reg_t, rcv_lnk, ==, 1, 10000))
271     if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS2_REG(interface), cvmx_pcsxx_status2_reg_t, xmtflt, ==, 0, 10000))
273     if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS2_REG(interface), cvmx_pcsxx_status2_reg_t, rcvflt, ==, 0, 10000))
278     cvmx_write_csr (CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
280     /* Clear all error interrupts before enabling the interface. */
281     cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0,interface), ~0x0ull);
282     cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), ~0x0ull);
283     cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), ~0x0ull);
286     gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
288     cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
295  * Bringup and enable a XAUI interface. After this call packet
299  * @param interface Interface to bring up
303 int __cvmx_helper_xaui_enable(int interface)
314         gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
315         gmxx_prtx_cfg.s.pknd = cvmx_helper_get_pknd(interface, 0);
316         cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmxx_prtx_cfg.u64);
319         bpid_map.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MAPX(0, interface));
321         bpid_map.s.bpid = cvmx_helper_get_bpid(interface, 0);
322         cvmx_write_csr(CVMX_GMXX_BPID_MAPX(0, interface), bpid_map.u64);
324         bpid_msk.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MSK(interface));
327         cvmx_write_csr(CVMX_GMXX_BPID_MSK(interface), bpid_msk.u64);
330         gmxx_txx_append_cfg.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface));
333         cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmxx_txx_append_cfg.u64);
336     __cvmx_helper_xaui_link_init(interface);
354     int interface = cvmx_helper_get_interface_num(ipd_port);
360     gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
361     gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
362     pcsxx_status1_reg.u64 = cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
376             int qlm = (interface == 1) ? 0 : interface;
385             int qlm = cvmx_qlm_interface(interface);
391         misc_ctl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
393             __cvmx_helper_xaui_link_init(interface);
398         cvmx_write_csr (CVMX_GMXX_RXX_INT_EN(0,interface), 0x0);
399         cvmx_write_csr (CVMX_GMXX_TX_INT_EN(interface), 0x0);
400         cvmx_write_csr (CVMX_PCSXX_INT_EN_REG(interface), 0x0);
421     int interface = cvmx_helper_get_interface_num(ipd_port);
425     gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
426     gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
437     return __cvmx_helper_xaui_link_init(interface);
457     int interface = cvmx_helper_get_interface_num(ipd_port);
462     pcsxx_control1_reg.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
464     cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), pcsxx_control1_reg.u64);
467     gmxx_xaui_ext_loopback.u64 = cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface));
469     cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface), gmxx_xaui_ext_loopback.u64);
472     return __cvmx_helper_xaui_link_init(interface);