Lines Matching refs:tmpReg
226 uint32_t status, mask, tmpReg=0;
242 tmpReg = GET_UINT32(p_Fm->p_FmDmaRegs->fmdmtcid);
250 hardwarePortId = (uint8_t)(((tmpReg & DMA_TRANSFER_PORTID_MASK) >> DMA_TRANSFER_PORTID_SHIFT));
252 tnum = (uint8_t)((tmpReg & DMA_TRANSFER_TNUM_MASK) >> DMA_TRANSFER_TNUM_SHIFT);
253 liodn = (uint16_t)(tmpReg & DMA_TRANSFER_LIODN_MASK);
355 uint32_t tmpReg;
375 tmpReg = (integer << FPM_TS_INT_SHIFT) | (uint16_t)fraction;
376 WRITE_UINT32(p_Fm->p_FmFpmRegs->fpmtsc2, tmpReg);
1350 uint32_t tmpReg = 0;
1379 tmpReg = (uint32_t)(hardwarePortId << FPM_PORT_FM_CTL_PORTID_SHIFT);
1384 tmpReg = FPM_PORT_FM_CTL2 | FPM_PORT_FM_CTL1;
1388 tmpReg |= (FPM_PORT_FM_CTL1 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT) | FPM_PORT_FM_CTL1;
1390 tmpReg |= (FPM_PORT_FM_CTL2 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT) | FPM_PORT_FM_CTL2;
1392 WRITE_UINT32(p_Fm->p_FmFpmRegs->fpmpr, tmpReg);
1401 uint32_t tmpReg;
1486 tmpReg = GET_UINT32(p_Fm->p_FmQmiRegs->fmqm_gc);
1487 enqTh = (uint8_t)(tmpReg>>8);
1492 tmpReg &= ~QMI_CFG_ENQ_MASK;
1493 tmpReg |= ((uint32_t)enqTh << 8);
1497 deqTh = (uint8_t)tmpReg;
1503 tmpReg &= ~QMI_CFG_DEQ_MASK;
1504 tmpReg |= (uint32_t)deqTh;
1508 WRITE_UINT32(p_Fm->p_FmQmiRegs->fmqm_gc, tmpReg);
1549 tmpReg = (uint32_t)(hardwarePortId << FPM_PORT_FM_CTL_PORTID_SHIFT);
1553 tmpReg |= (FPM_PORT_FM_CTL1 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT) |FPM_PORT_FM_CTL1;
1555 tmpReg |= (FPM_PORT_FM_CTL2 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT) |FPM_PORT_FM_CTL2;
1559 tmpReg |= (FPM_PORT_FM_CTL2|FPM_PORT_FM_CTL1);
1563 tmpReg |= (FPM_PORT_FM_CTL1 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT);
1565 tmpReg |= (FPM_PORT_FM_CTL2 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT);
1567 WRITE_UINT32(p_Fm->p_FmFpmRegs->fpmpr, tmpReg);
1578 tmpReg = GET_UINT32(p_Fm->p_FmDmaRegs->fmdmplr[hardwarePortId/2]);
1581 tmpReg &= ~FM_LIODN_BASE_MASK;
1582 tmpReg |= (uint32_t)p_PortParams->liodnBase;
1586 tmpReg &= ~(FM_LIODN_BASE_MASK<< DMA_LIODN_SHIFT);
1587 tmpReg |= (uint32_t)p_PortParams->liodnBase << DMA_LIODN_SHIFT;
1589 WRITE_UINT32(p_Fm->p_FmDmaRegs->fmdmplr[hardwarePortId/2], tmpReg);
1602 uint32_t tmpReg;
1642 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_pp[hardwarePortId-1]);
1644 numOfTasks = (uint8_t)(((tmpReg & BMI_NUM_OF_TASKS_MASK) >> BMI_NUM_OF_TASKS_SHIFT) + 1);
1649 ASSERT_COND(p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas >= ((tmpReg & BMI_NUM_OF_DMAS_MASK) >> BMI_NUM_OF_DMAS_SHIFT) + 1);
1650 p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas -= (((tmpReg & BMI_NUM_OF_DMAS_MASK) >> BMI_NUM_OF_DMAS_SHIFT) + 1);
1653 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK;
1654 tmpReg |= (uint32_t)(p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas + p_Fm->p_FmStateStruct->extraOpenDmasPoolSize - 1) << BMI_CFG2_DMAS_SHIFT;
1655 WRITE_UINT32(p_Fm->p_FmBmiRegs->fmbm_cfg2, tmpReg);
1658 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_pfs[hardwarePortId-1]);
1660 (((tmpReg & BMI_FIFO_SIZE_MASK) + 1) * BMI_FIFO_UNITS));
1662 (((tmpReg & BMI_FIFO_SIZE_MASK) + 1) * BMI_FIFO_UNITS);
1688 tmpReg = GET_UINT32(p_Fm->p_FmQmiRegs->fmqm_gc);
1695 tmpReg &= ~QMI_CFG_ENQ_MASK;
1696 tmpReg |= ((uint32_t)enqTh << QMI_CFG_ENQ_SHIFT);
1701 tmpReg &= ~QMI_CFG_DEQ_MASK;
1702 tmpReg |= (uint32_t)deqTh;
1704 WRITE_UINT32(p_Fm->p_FmQmiRegs->fmqm_gc, tmpReg);
1718 uint32_t tmpReg;
1747 tmpReg = GET_UINT32(p_Fm->p_FmFpmRegs->fmfp_ps[hardwarePortId]);
1748 *p_IsStalled = (bool)!!(tmpReg & FPM_PS_STALLED);
1756 uint32_t tmpReg;
1790 tmpReg = (uint32_t)((hardwarePortId << FPM_PORT_FM_CTL_PORTID_SHIFT) | FPM_PRC_REALSE_STALLED);
1791 WRITE_UINT32(p_Fm->p_FmFpmRegs->fpmpr, tmpReg);
1963 uint32_t tmpReg;
1965 tmpReg = GET_UINT32(p_Fm->p_FmFpmRegs->fmrcr);
1966 if(tmpReg & FPM_RAM_CTL_RAMS_ECC_EN_SRC_SEL)
2028 uint32_t minFifoSizeRequired = 0, sizeOfFifo, tmpReg = 0;
2181 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_pfs[hardwarePortId-1]);
2183 oldVal = (uint16_t)((((tmpReg & BMI_EXTRA_FIFO_SIZE_MASK) + 1)*BMI_FIFO_UNITS) >> BMI_EXTRA_FIFO_SIZE_SHIFT);
2191 oldVal = (uint16_t)(((tmpReg & BMI_FIFO_SIZE_MASK) + 1)*BMI_FIFO_UNITS);
2204 tmpReg = (uint32_t)((sizeOfFifo/BMI_FIFO_UNITS - 1) |
2206 WRITE_UINT32(p_Fm->p_FmBmiRegs->fmbm_pfs[hardwarePortId-1], tmpReg);
2221 uint32_t tmpReg = 0;
2260 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_pp[hardwarePortId-1]);
2262 oldVal = (uint8_t)((tmpReg & BMI_NUM_OF_EXTRA_TASKS_MASK) >> BMI_EXTRA_NUM_OF_TASKS_SHIFT);
2270 oldVal = (uint8_t)(((tmpReg & BMI_NUM_OF_TASKS_MASK) >> BMI_NUM_OF_TASKS_SHIFT) + 1);
2285 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_pp[hardwarePortId-1]) & ~(BMI_NUM_OF_TASKS_MASK | BMI_NUM_OF_EXTRA_TASKS_MASK);
2286 tmpReg |= (uint32_t)(((numOfTasks-1) << BMI_NUM_OF_TASKS_SHIFT) |
2288 WRITE_UINT32(p_Fm->p_FmBmiRegs->fmbm_pp[hardwarePortId-1],tmpReg);
2303 uint32_t tmpReg = 0;
2342 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_pp[hardwarePortId-1]);
2344 oldVal = (uint8_t)((tmpReg & BMI_NUM_OF_EXTRA_DMAS_MASK) >> BMI_EXTRA_NUM_OF_DMAS_SHIFT);
2352 oldVal = (uint8_t)(((tmpReg & BMI_NUM_OF_DMAS_MASK) >> BMI_NUM_OF_DMAS_SHIFT) + 1);
2367 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_pp[hardwarePortId-1]) & ~(BMI_NUM_OF_DMAS_MASK | BMI_NUM_OF_EXTRA_DMAS_MASK);
2368 tmpReg |= (uint32_t)(((numOfOpenDmas-1) << BMI_NUM_OF_DMAS_SHIFT) |
2370 WRITE_UINT32(p_Fm->p_FmBmiRegs->fmbm_pp[hardwarePortId-1], tmpReg);
2373 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK;
2374 tmpReg |= (uint32_t)(p_Fm->p_FmStateStruct->accumulatedNumOfOpenDmas + p_Fm->p_FmStateStruct->extraOpenDmasPoolSize - 1) << BMI_CFG2_DMAS_SHIFT;
2375 WRITE_UINT32(p_Fm->p_FmBmiRegs->fmbm_cfg2, tmpReg);
2596 uint32_t tmpReg, cfgReg = 0;
2808 tmpReg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC | DMA_STATUS_SYSTEM_WRITE_ECC | DMA_STATUS_FM_WRITE_ECC);
2809 /*tmpReg |= (DMA_STATUS_SYSTEM_DPEXT_ECC | DMA_STATUS_FM_DPEXT_ECC | DMA_STATUS_SYSTEM_DPDAT_ECC | DMA_STATUS_FM_DPDAT_ECC | DMA_STATUS_FM_SPDAT_ECC);*/
2810 WRITE_UINT32(p_Fm->p_FmDmaRegs->fmdmsr, GET_UINT32(p_Fm->p_FmDmaRegs->fmdmsr) | tmpReg);
2813 tmpReg = 0;
2814 tmpReg |= p_FmDriverParam->dmaCacheOverride << DMA_MODE_CACHE_OR_SHIFT;
2816 tmpReg |= DMA_MODE_AID_OR;
2818 tmpReg |= DMA_MODE_BER;
2820 tmpReg |= DMA_MODE_ECC;
2822 tmpReg |= DMA_MODE_SBER;
2823 tmpReg |= (uint32_t)(p_FmDriverParam->dmaAxiDbgNumOfBeats - 1) << DMA_MODE_AXI_DBG_SHIFT;
2826 tmpReg |= p_FmDriverParam->dmaEmergency.emergencyBusSelect;
2827 tmpReg |= p_FmDriverParam->dmaEmergency.emergencyLevel << DMA_MODE_EMERGENCY_LEVEL_SHIFT;
2831 tmpReg |= ((p_FmDriverParam->dmaCamNumOfEntries/DMA_CAM_UNITS) - 1) << DMA_MODE_CEN_SHIFT;
2833 tmpReg |= DMA_MODE_SECURE_PROT;
2834 tmpReg |= p_FmDriverParam->dmaDbgCntMode << DMA_MODE_DBG_SHIFT;
2835 tmpReg |= p_FmDriverParam->dmaAidMode << DMA_MODE_AID_MODE_SHIFT;
2838 tmpReg |= DMA_MODE_EMERGENCY_READ;
2841 WRITE_UINT32(p_Fm->p_FmDmaRegs->fmdmmr, tmpReg);
2844 tmpReg = ((uint32_t)p_FmDriverParam->dmaCommQThresholds.assertEmergency << DMA_THRESH_COMMQ_SHIFT) |
2847 WRITE_UINT32(p_Fm->p_FmDmaRegs->fmdmtr, tmpReg);
2850 tmpReg = ((uint32_t)p_FmDriverParam->dmaCommQThresholds.clearEmergency << DMA_THRESH_COMMQ_SHIFT) |
2853 WRITE_UINT32(p_Fm->p_FmDmaRegs->fmdmhy, tmpReg);
2882 tmpReg = (((uint32_t)p_FmDriverParam->liodnBasePerPort[i] << DMA_LIODN_SHIFT) |
2884 WRITE_UINT32(p_Fm->p_FmDmaRegs->fmdmplr[i/2], tmpReg);
2892 tmpReg = (uint32_t)(p_FmDriverParam->thresholds.dispLimit << FPM_DISP_LIMIT_SHIFT);
2893 WRITE_UINT32(p_Fm->p_FmFpmRegs->fpmflc, tmpReg);
2895 tmpReg = (((uint32_t)p_FmDriverParam->thresholds.prsDispTh << FPM_THR1_PRS_SHIFT) |
2899 WRITE_UINT32(p_Fm->p_FmFpmRegs->fpmdis1, tmpReg);
2901 tmpReg = (((uint32_t)p_FmDriverParam->thresholds.qmiEnqDispTh << FPM_THR2_QMI_ENQ_SHIFT) |
2905 WRITE_UINT32(p_Fm->p_FmFpmRegs->fpmdis2, tmpReg);
2908 tmpReg = 0;
2910 tmpReg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC | FPM_EV_MASK_SINGLE_ECC);
2913 tmpReg |= FPM_EV_MASK_STALL_EN;
2915 tmpReg |= FPM_EV_MASK_SINGLE_ECC_EN;
2917 tmpReg |= FPM_EV_MASK_DOUBLE_ECC_EN;
2918 tmpReg |= (p_Fm->p_FmDriverParam->catastrophicErr << FPM_EV_MASK_CAT_ERR_SHIFT);
2919 tmpReg |= (p_Fm->p_FmDriverParam->dmaErr << FPM_EV_MASK_DMA_ERR_SHIFT);
2921 tmpReg |= FPM_EV_MASK_EXTERNAL_HALT;
2923 tmpReg |= FPM_EV_MASK_ECC_ERR_HALT;
2924 WRITE_UINT32(p_Fm->p_FmFpmRegs->fpmem, tmpReg);
2933 tmpReg = 0;
2935 tmpReg = (FPM_RAM_CTL_MURAM_ECC | FPM_RAM_CTL_IRAM_ECC);
2938 tmpReg |= FPM_RAM_CTL_RAMS_ECC_EN_SRC_SEL;
2942 tmpReg |= FPM_RAM_CTL_MURAM_TEST_ECC;
2944 tmpReg |= FPM_RAM_CTL_IRAM_TEST_ECC;
2945 WRITE_UINT32(p_Fm->p_FmFpmRegs->fmrcr, tmpReg);
2947 tmpReg = 0;
2950 tmpReg |= FPM_IRAM_ECC_ERR_EX_EN;
2955 tmpReg |= FPM_MURAM_ECC_ERR_EX_EN;
2958 WRITE_UINT32(p_Fm->p_FmFpmRegs->fmrie, tmpReg);
2975 tmpReg = (uint32_t)(XX_VirtToPhys(UINT_TO_PTR(p_Fm->fifoBaseAddr)) - p_Fm->fmMuramPhysBaseAddr);
2976 tmpReg = tmpReg / BMI_FIFO_ALIGN;
2978 tmpReg |= ((p_Fm->p_FmStateStruct->totalFifoSize/BMI_FIFO_UNITS - 1) << BMI_CFG1_FIFO_SIZE_SHIFT);
2979 WRITE_UINT32(p_Fm->p_FmBmiRegs->fmbm_cfg1, tmpReg);
2981 tmpReg = ((uint32_t)(p_Fm->p_FmStateStruct->totalNumOfTasks - 1) << BMI_CFG2_TASKS_SHIFT );
2983 WRITE_UINT32(p_Fm->p_FmBmiRegs->fmbm_cfg2, tmpReg);
2986 tmpReg = 0;
2992 tmpReg |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
2994 tmpReg |= BMI_ERR_INTR_EN_PIPELINE_ECC;
2996 tmpReg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
2998 tmpReg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
2999 WRITE_UINT32(p_Fm->p_FmBmiRegs->fmbm_ier, tmpReg);
3006 tmpReg = 0;
3008 tmpReg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
3010 tmpReg |= QMI_ERR_INTR_EN_DOUBLE_ECC;
3012 WRITE_UINT32(p_Fm->p_FmQmiRegs->fmqm_eien, tmpReg);
3021 tmpReg = (uint32_t)((periodInFmClocks/64) + 1);
3024 tmpReg = (uint32_t)(periodInFmClocks/64);
3025 if(!tmpReg)
3026 tmpReg = 1;
3028 tmpReg <<= QMI_TAPC_TAP;
3029 WRITE_UINT32(p_Fm->p_FmQmiRegs->fmqm_tapc, tmpReg);
3032 tmpReg = 0;
3036 tmpReg |= QMI_INTR_EN_SINGLE_ECC;
3038 WRITE_UINT32(p_Fm->p_FmQmiRegs->fmqm_ien, tmpReg);
3771 /* Add this port to tmpReg */
3786 uint32_t tmpReg;
3816 tmpReg = GET_UINT32(p_Fm->p_FmFpmRegs->fmrcr);
3817 if(tmpReg & FPM_RAM_CTL_RAMS_ECC_EN_SRC_SEL)
3820 WRITE_UINT32(p_Fm->p_FmFpmRegs->fmrcr, tmpReg | FPM_RAM_CTL_IRAM_ECC_EN);
3823 WRITE_UINT32(p_Fm->p_FmFpmRegs->fmrcr, tmpReg | (FPM_RAM_CTL_RAMS_ECC_EN | FPM_RAM_CTL_IRAM_ECC_EN));
3833 uint32_t tmpReg;
3873 tmpReg = GET_UINT32(p_Fm->p_FmFpmRegs->fmrcr);
3874 if(tmpReg & FPM_RAM_CTL_RAMS_ECC_EN_SRC_SEL)
3877 WRITE_UINT32(p_Fm->p_FmFpmRegs->fmrcr, tmpReg & ~FPM_RAM_CTL_IRAM_ECC_EN);
3880 WRITE_UINT32(p_Fm->p_FmFpmRegs->fmrcr, tmpReg & ~(FPM_RAM_CTL_RAMS_ECC_EN | FPM_RAM_CTL_IRAM_ECC_EN));
3891 uint32_t tmpReg;
3907 tmpReg = GET_UINT32(p_Fm->p_FmDmaRegs->fmdmmr);
3909 tmpReg |= DMA_MODE_BER;
3911 tmpReg &= ~DMA_MODE_BER;
3913 WRITE_UINT32(p_Fm->p_FmDmaRegs->fmdmmr, tmpReg);
3918 tmpReg = GET_UINT32(p_Fm->p_FmDmaRegs->fmdmmr);
3920 tmpReg |= DMA_MODE_ECC;
3922 tmpReg &= ~DMA_MODE_ECC;
3923 WRITE_UINT32(p_Fm->p_FmDmaRegs->fmdmmr, tmpReg);
3926 tmpReg = GET_UINT32(p_Fm->p_FmFpmRegs->fpmem);
3928 tmpReg |= FPM_EV_MASK_STALL_EN;
3930 tmpReg &= ~FPM_EV_MASK_STALL_EN;
3931 WRITE_UINT32(p_Fm->p_FmFpmRegs->fpmem, tmpReg);
3934 tmpReg = GET_UINT32(p_Fm->p_FmFpmRegs->fpmem);
3936 tmpReg |= FPM_EV_MASK_SINGLE_ECC_EN;
3938 tmpReg &= ~FPM_EV_MASK_SINGLE_ECC_EN;
3939 WRITE_UINT32(p_Fm->p_FmFpmRegs->fpmem, tmpReg);
3942 tmpReg = GET_UINT32(p_Fm->p_FmFpmRegs->fpmem);
3944 tmpReg |= FPM_EV_MASK_DOUBLE_ECC_EN;
3946 tmpReg &= ~FPM_EV_MASK_DOUBLE_ECC_EN;
3947 WRITE_UINT32(p_Fm->p_FmFpmRegs->fpmem, tmpReg);
3950 tmpReg = GET_UINT32(p_Fm->p_FmQmiRegs->fmqm_ien);
3962 tmpReg |= QMI_INTR_EN_SINGLE_ECC;
3965 tmpReg &= ~QMI_INTR_EN_SINGLE_ECC;
3966 WRITE_UINT32(p_Fm->p_FmQmiRegs->fmqm_ien, tmpReg);
3969 tmpReg = GET_UINT32(p_Fm->p_FmQmiRegs->fmqm_eien);
3981 tmpReg |= QMI_ERR_INTR_EN_DOUBLE_ECC;
3984 tmpReg &= ~QMI_ERR_INTR_EN_DOUBLE_ECC;
3985 WRITE_UINT32(p_Fm->p_FmQmiRegs->fmqm_eien, tmpReg);
3988 tmpReg = GET_UINT32(p_Fm->p_FmQmiRegs->fmqm_eien);
3990 tmpReg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
3992 tmpReg &= ~QMI_ERR_INTR_EN_DEQ_FROM_DEF;
3993 WRITE_UINT32(p_Fm->p_FmQmiRegs->fmqm_eien, tmpReg);
3996 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_ier);
4008 tmpReg |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
4011 tmpReg &= ~BMI_ERR_INTR_EN_LIST_RAM_ECC;
4012 WRITE_UINT32(p_Fm->p_FmBmiRegs->fmbm_ier, tmpReg);
4015 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_ier);
4027 tmpReg |= BMI_ERR_INTR_EN_PIPELINE_ECC;
4030 tmpReg &= ~BMI_ERR_INTR_EN_PIPELINE_ECC;
4031 WRITE_UINT32(p_Fm->p_FmBmiRegs->fmbm_ier, tmpReg);
4034 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_ier);
4036 tmpReg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
4038 tmpReg &= ~BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
4039 WRITE_UINT32(p_Fm->p_FmBmiRegs->fmbm_ier, tmpReg);
4042 tmpReg = GET_UINT32(p_Fm->p_FmBmiRegs->fmbm_ier);
4054 tmpReg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
4057 tmpReg &= ~BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
4058 WRITE_UINT32(p_Fm->p_FmBmiRegs->fmbm_ier, tmpReg);
4061 tmpReg = GET_UINT32(p_Fm->p_FmFpmRegs->fmrie);
4067 tmpReg |= FPM_IRAM_ECC_ERR_EX_EN;
4073 tmpReg &= ~FPM_IRAM_ECC_ERR_EX_EN;
4075 WRITE_UINT32(p_Fm->p_FmFpmRegs->fmrie, tmpReg);
4079 tmpReg = GET_UINT32(p_Fm->p_FmFpmRegs->fmrie);
4085 tmpReg |= FPM_MURAM_ECC_ERR_EX_EN;
4091 tmpReg &= ~FPM_MURAM_ECC_ERR_EX_EN;
4094 WRITE_UINT32(p_Fm->p_FmFpmRegs->fmrie, tmpReg);
4109 uint32_t tmpReg;
4141 tmpReg = GET_UINT32(p_Fm->p_FmFpmRegs->fm_ip_rev_1);
4142 p_FmRevisionInfo->majorRev = (uint8_t)((tmpReg & FPM_REV1_MAJOR_MASK) >> FPM_REV1_MAJOR_SHIFT);
4143 p_FmRevisionInfo->minorRev = (uint8_t)((tmpReg & FPM_REV1_MINOR_MASK) >> FPM_REV1_MINOR_SHIFT);
4330 uint32_t tmpReg;
4372 tmpReg = GET_UINT32(p_Fm->p_FmDmaRegs->fmdmsr);
4374 p_FmDmaStatus->cmqNotEmpty = (bool)(tmpReg & DMA_STATUS_CMD_QUEUE_NOT_EMPTY);
4375 p_FmDmaStatus->busError = (bool)(tmpReg & DMA_STATUS_BUS_ERR);
4376 p_FmDmaStatus->readBufEccError = (bool)(tmpReg & DMA_STATUS_READ_ECC);
4377 p_FmDmaStatus->writeBufEccSysError = (bool)(tmpReg & DMA_STATUS_SYSTEM_WRITE_ECC);
4378 p_FmDmaStatus->writeBufEccFmError = (bool)(tmpReg & DMA_STATUS_FM_WRITE_ECC);
4436 uint32_t tmpReg;
4443 tmpReg = GET_UINT32(p_Fm->p_FmFpmRegs->fpmem);
4444 /* clear tmpReg event bits in order not to clear standing events */
4445 tmpReg &= ~(FPM_EV_MASK_DOUBLE_ECC | FPM_EV_MASK_STALL | FPM_EV_MASK_SINGLE_ECC);
4446 WRITE_UINT32(p_Fm->p_FmFpmRegs->fpmem, tmpReg | FPM_EV_MASK_RELEASE_FM);