xscale/ixp425/if_npe.c

206 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val)
457 		WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]);
458 		WR4(sc, NPE_MAC_ADDR(i), addr[i]);
657 	WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
660 	WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
962 	WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]);
963 	WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]);
964 	WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]);
965 	WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]);
966 	WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]);
967 	WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]);
1228  	WR4(sc, NPE_MAC_RX_CNTRL1,
1230  	WR4(sc, NPE_MAC_TX_CNTRL1,
1236 	WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1);	/* clock ratio: for ipx4xx */
1237 	WR4(sc, NPE_MAC_TX_CNTRL2,	0xf);	/* max retries */
1238 	WR4(sc, NPE_MAC_RANDOM_SEED,	0x8);	/* LFSR back-off seed */
1240 	WR4(sc, NPE_MAC_THRESH_P_EMPTY,	0x12);
1241 	WR4(sc, NPE_MAC_THRESH_P_FULL,	0x30);
1242 	WR4(sc, NPE_MAC_BUF_SIZE_TX,	0x8);	/* tx fifo threshold (bytes) */
1243 	WR4(sc, NPE_MAC_TX_DEFER,	0x15);	/* for single deferral */
1244 	WR4(sc, NPE_MAC_RX_DEFER,	0x16);	/* deferral on inter-frame gap*/
1245 	WR4(sc, NPE_MAC_TX_TWO_DEFER_1,	0x8);	/* for 2-part deferral */
1246 	WR4(sc, NPE_MAC_TX_TWO_DEFER_2,	0x7);	/* for 2-part deferral */
1247 	WR4(sc, NPE_MAC_SLOT_TIME,	0x80);	/* assumes MII mode */
1249 	WR4(sc, NPE_MAC_TX_CNTRL1,
1256 	WR4(sc, NPE_MAC_RX_CNTRL1, NPE_RX_CNTRL1_PAUSE_EN);
1257 	WR4(sc, NPE_MAC_RX_CNTRL2, 0);
1271  	WR4(sc, NPE_MAC_RX_CNTRL1,
1273  	WR4(sc, NPE_MAC_TX_CNTRL1,
1433  	WR4(sc, NPE_MAC_RX_CNTRL1,
1435  	WR4(sc, NPE_MAC_TX_CNTRL1,
1453 	WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);
1455 	WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT);
1456 	WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN);
1748 	WR4(sc, NPE_MAC_RX_CNTRL1, rx1);
1749 	WR4(sc, NPE_MAC_TX_CNTRL1, tx1);