ti/omap4/omap4_prcm_clks.c

517 	uint32_t clksel;
536 	clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
537 	clksel &= ~CLKCTRL_MODULEMODE_MASK;
538 	clksel |=  clk_details->enable_mode;
539 	bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel);
547 		clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
548 		if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED)
554 	if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) {
556 		printf("Error: 0x%08x => 0x%08x\n", clk_details->clksel_reg, clksel);
583 	uint32_t clksel;
602 	clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
603 	clksel &= ~CLKCTRL_MODULEMODE_MASK;
604 	clksel |=  CLKCTRL_MODULEMODE_DISABLE;
605 	bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel);
652 	uint32_t clksel;
668 	clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
671 	if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED)
772 	uint32_t clksel;
790 	clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
791 	if (clksel & (0x1UL << 24))
822 	uint32_t clksel;
848 	clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
852 		clksel &= ~(0x1UL << 24);
854 		clksel |= (0x1UL << 24);
858 	bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel);
883 	uint32_t clksel;
904 		clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg);
905 		if (clksel & (0x1UL << 24))
940 	uint32_t clksel;
949 	clksel = bus_read_4(sc->sc_res, CM_SYS_CLKSEL_OFFSET);
950 	switch (clksel & 0x7) {
998 	uint32_t clksel;
1007 	/* Read the clksel register which contains the DPLL multiple and divide
1010 	clksel = bus_read_4(sc->sc_res, CM_CLKSEL_DPLL_MPU);
1012 	pll_mult = ((clksel >> 8) & 0x7ff);
1013 	pll_div = (clksel & 0x7f) + 1;
1084 	uint32_t clksel;
1106 		clksel = bus_read_4(clk_mem_res, clksel_reg_off);
1107 		clksel &= ~CLKCTRL_MODULEMODE_MASK;
1108 		clksel |=  CLKCTRL_MODULEMODE_ENABLE;
1110 		clksel |= (0x1 << 8); /* USB-HOST optional clock: USB_CH0_CLK */
1111 		clksel |= (0x1 << 9); /* USB-HOST optional clock: USB_CH1_CLK */
1137 		clksel = bus_read_4(clk_mem_res, clksel_reg_off);
1140 			clksel &= ~CLKCTRL_MODULEMODE_MASK;
1141 			clksel |=  /*CLKCTRL_MODULEMODE_ENABLE*/2;
1143 			clksel |= (0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */
1147 			clksel |= (0x1 << 8);  /* UTMI_P1_CLK */
1149 			clksel |= (0x1 << 9);  /* UTMI_P2_CLK */
1152 			clksel |= (0x5 << 11);  /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */
1154 			clksel |= (0x5 << 12);  /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */
1162 	bus_write_4(clk_mem_res, clksel_reg_off, clksel);
1166 		clksel = bus_read_4(clk_mem_res, clksel_reg_off);
1167 		if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED)
1172 	if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) {
1174 		printf("Error: 0x%08x => 0x%08x\n", clksel_reg_off, clksel);
1200 	uint32_t clksel;
1212 		clksel = bus_read_4(clk_mem_res, clksel_reg_off);
1213 		clksel &= ~CLKCTRL_MODULEMODE_MASK;
1214 		clksel |=  CLKCTRL_MODULEMODE_DISABLE;
1240 		clksel = bus_read_4(clk_mem_res, clksel_reg_off);
1244 			clksel &= ~CLKCTRL_MODULEMODE_MASK;
1245 			clksel |=  CLKCTRL_MODULEMODE_DISABLE;
1247 			clksel &= ~(0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */
1251 			clksel &= ~(0x1 << 8);  /* UTMI_P1_CLK */
1253 			clksel &= ~(0x1 << 9);  /* UTMI_P2_CLK */
1256 			clksel &= ~(0x5 << 11);  /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */
1258 			clksel &= ~(0x5 << 12);  /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */
1266 	bus_write_4(clk_mem_res, clksel_reg_off, clksel);
1291 	uint32_t clksel;
1311 	clksel = bus_read_4(clk_mem_res, clksel_reg_off);
1314 	if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED)
1341 	uint32_t clksel;
1358 	clksel = bus_read_4(clk_mem_res, clksel_reg_off);
1362 		clksel |= (0x1 << bit);
1364 		clksel &= ~(0x1 << bit);
1366 	bus_write_4(clk_mem_res, clksel_reg_off, clksel);