arm/include/cpu-v6.h

90 #define _WF1(fname, aname...)						\
115 _WF1(_CP15_TLBIASID, CP15_TLBIASID(%0))		/* Invalidate unified TLB by ASID */
117 _WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0))	/* Invalidate unified TLB by ASID IS */
119 _WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0))		/* Invalidate unified TLB by MVA, all ASID */
121 _WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0))	/* Invalidate unified TLB by MVA, all ASID IS */
123 _WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0))		/* Invalidate unified TLB by MVA */
125 _WF1(_CP15_TTB_SET, CP15_TTBR0(%0))
133 _WF1(_CP15_BPIMVA, CP15_BPIMVA(%0))		/* Branch predictor invalidate by MVA */
134 _WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0))		/* Data cache clean and invalidate by MVA PoC */
135 _WF1(_CP15_DCCISW, CP15_DCCISW(%0))		/* Data cache clean and invalidate by set/way */
136 _WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0))		/* Data cache clean by MVA PoC */
138 _WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0))		/* Data cache clean by MVA PoU */
140 _WF1(_CP15_DCCSW, CP15_DCCSW(%0))		/* Data cache clean by set/way */
141 _WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0))		/* Data cache invalidate by MVA PoC */
142 _WF1(_CP15_DCISW, CP15_DCISW(%0))		/* Data cache invalidate by set/way */
147 _WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0))		/* Instruction cache invalidate */
160 _WF1(cp14_dbgdscr_v6_set, CP14_DBGDSCRext_V6(%0))
161 _WF1(cp14_dbgdscr_v7_set, CP14_DBGDSCRext_V7(%0))
162 _WF1(cp14_dbgvcr_set, CP14_DBGVCR(%0))
163 _WF1(cp14_dbgoslar_set, CP14_DBGOSLAR(%0))
168 _WF1(cp15_cpacr_set, CP15_CPACR(%0))
171 _WF1(cp15_prrr_set, CP15_PRRR(%0))
172 _WF1(cp15_nmrr_set, CP15_NMRR(%0))
180 _WF1(cp15_actlr_set, CP15_ACTLR(%0))
181 _WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0))
182 _WF1(cp15_ats1cpw_set, CP15_ATS1CPW(%0))
183 _WF1(cp15_ats1cur_set, CP15_ATS1CUR(%0))
184 _WF1(cp15_ats1cuw_set, CP15_ATS1CUW(%0))
198 _WF1(cp15_csselr_set, CP15_CSSELR(%0))
219 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
221 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
223 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
226 _WF1(cp15_pmcr_set, CP15_PMCR(%0))
228 _WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0))
229 _WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0))
231 _WF1(cp15_pmovsr_set, CP15_PMOVSR(%0))
232 _WF1(cp15_pmswinc_set, CP15_PMSWINC(%0))
234 _WF1(cp15_pmselr_set, CP15_PMSELR(%0))
236 _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
238 _WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0))
240 _WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0))
242 _WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
244 _WF1(cp15_pminten_set, CP15_PMINTENSET(%0))
245 _WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0))
249 _WF1(cp15_tpidrurw_set, CP15_TPIDRURW(%0))
251 _WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0))
253 _WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0))
257 _WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0))
259 _WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0))
261 _WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0))
263 _WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0))
265 _WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0))
267 _WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0))
269 _WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0))
271 _WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0))
273 _WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0))
289 #undef	_WF1