Lines Matching refs:size
123 * and size values which are not aligned to cacheline boundaries; the armv4 and
135 icache_sync(vm_offset_t va, vm_size_t size)
137 cpu_icache_sync_range(va, size);
141 dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
144 cpu_dcache_inv_range(va, size);
146 cpu_l2cache_inv_range(pa, size);
148 cpu_l2cache_inv_range(va, size);
153 dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
158 cpu_l2cache_inv_range(pa, size);
160 cpu_l2cache_inv_range(va, size);
162 cpu_dcache_inv_range(va, size);
166 dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
169 cpu_dcache_wb_range(va, size);
171 cpu_l2cache_wb_range(pa, size);
173 cpu_l2cache_wb_range(va, size);