cavium/cns11xx/econa.c

53 static struct econa_softc *econa_softc;
190 econa_cpu_add_builtin_children(device_t dev, struct econa_softc *sc)
238 read_4(struct econa_softc *sc, bus_size_t off)
245 write_4(struct econa_softc *sc, bus_size_t off, uint32_t val)
252 system_read_4(struct econa_softc *sc, bus_size_t off)
259 system_write_4(struct econa_softc *sc, bus_size_t off, uint32_t val)
268 econa_set_irq_mode(struct econa_softc * sc, unsigned int irq,
298 econa_set_irq_level(struct econa_softc * sc,
330 	uint32_t sclock = system_read_4(econa_softc, SYSTEM_CLOCK);
355 	struct econa_softc *sc = device_get_softc(dev);
360 	econa_softc = sc;
413 	struct econa_softc *sc = device_get_softc(dev);
545 	value = read_4(econa_softc,INTC_INTERRUPT_MASK_REG_OFFSET) | 1<<nb;
546 	write_4(econa_softc, INTC_INTERRUPT_MASK_REG_OFFSET, value);
554 	value = read_4(econa_softc,
556 	write_4(econa_softc,
558 	value = read_4(econa_softc, INTC_INTERRUPT_MASK_REG_OFFSET)& ~(1 << nb);
559 	write_4(econa_softc, INTC_INTERRUPT_MASK_REG_OFFSET, value);
567 	irq = read_4(econa_softc, INTC_INTERRUPT_STATUS_REG_OFFSET) &
568 	    ~(read_4(econa_softc, INTC_INTERRUPT_MASK_REG_OFFSET));
582 	control = system_read_4(econa_softc, RESET_CONTROL);
584 	system_write_4(econa_softc, RESET_CONTROL, control);
585 	control = system_read_4(econa_softc, RESET_CONTROL);
587 	system_write_4(econa_softc, RESET_CONTROL, control);
599 	cfg_reg =  system_read_4(econa_softc, RESET_CONTROL);
602 	system_write_4(econa_softc, RESET_CONTROL, cfg_reg);
608 	cfg_reg =  system_read_4(econa_softc, RESET_CONTROL);
610 	system_write_4(econa_softc, RESET_CONTROL, cfg_reg);
615 	cfg_reg = system_read_4(econa_softc, RESET_CONTROL);
618 	system_write_4(econa_softc, RESET_CONTROL, cfg_reg);
648 	sizeof(struct econa_softc),