X86/AsmParser/X86AsmParser.cpp

265     unsigned BaseReg, IndexReg, TmpReg, Scale;
275       State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
280     unsigned getIndexReg() { return IndexReg; }
383           // If we already have a BaseReg, then assume this is the IndexReg with
388             assert (!IndexReg && "BaseReg/IndexReg already set!");
389             IndexReg = TmpReg;
420           // If we already have a BaseReg, then assume this is the IndexReg with
425             assert (!IndexReg && "BaseReg/IndexReg already set!");
426             IndexReg = TmpReg;
462           assert (!IndexReg && "IndexReg already set!");
464           IndexReg = Reg;
512           assert (!IndexReg && "IndexReg already set!");
513           IndexReg = TmpReg;
599           // If we already have a BaseReg, then assume this is the IndexReg with
604             assert (!IndexReg && "BaseReg/IndexReg already set!");
605             IndexReg = TmpReg;
713                         unsigned IndexReg, unsigned Scale, SMLoc Start,
832 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg,
836   // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
837   if (BaseReg != 0 && IndexReg != 0) {
839         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
840          X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
841         IndexReg != X86::RIZ) {
846         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
847          X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
848         IndexReg != X86::EIZ){
853       if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
854           X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
859            IndexReg != X86::SI && IndexReg != X86::DI) ||
861            IndexReg != X86::BX && IndexReg != X86::BP)) {
1015                                /*BaseReg=*/basereg, /*IndexReg=*/0, /*Scale=*/1,
1024                                /*BaseReg=*/basereg, /*IndexReg=*/0, /*Scale=*/1,
1067     unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1106                                IndexReg, Scale, Start, End, Size, Identifier,
1120   // bracketed expression (i.e., ImmDisp [ BaseReg + Scale*IndexReg + Disp])
1305   // Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ].  We
1344   int IndexReg = SM.getIndexReg();
1348     if (!BaseReg && !IndexReg) {
1355     if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
1360                                  IndexReg, Scale, Start, End, Size);
1364   return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1442                                    /*BaseReg=*/0, /*IndexReg=*/0, /*Scale=*/1,
1464   return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0,/*IndexReg=*/0,
1513   // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1533     return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0, /*IndexReg=*/0,
1562                                /*BaseReg=*/1, /*IndexReg=*/0, /*Scale=*/1,
1751     // Parse ImmDisp [ BaseReg + Scale*IndexReg + Disp ].
1958   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
1984       if (ParseRegister(IndexReg, L, L)) return nullptr;
2053       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
2059   if (CheckBaseRegAndIndexReg(BaseReg, IndexReg, ErrMsg)) {
2064   if (SegReg || BaseReg || IndexReg)
2066                                  IndexReg, Scale, MemStart, MemEnd);
2259         Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2271         Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {