Target/Mips/MipsSEInstrInfo.cpp

182                 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
189   if (Mips::GPR32RegClass.hasSubClassEq(RC))
191   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
193   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
195   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
197   else if (Mips::ACC128RegClass.hasSubClassEq(RC))
199   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
201   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
203   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
205   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
207   else if (RC->hasType(MVT::v16i8))
209   else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
211   else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
213   else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
215   else if (Mips::LO32RegClass.hasSubClassEq(RC))
217   else if (Mips::LO64RegClass.hasSubClassEq(RC))
219   else if (Mips::HI32RegClass.hasSubClassEq(RC))
221   else if (Mips::HI64RegClass.hasSubClassEq(RC))
228     if (Mips::HI32RegClass.hasSubClassEq(RC)) {
231     } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
234     } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
237     } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
250                  unsigned DestReg, int FI, const TargetRegisterClass *RC,
262   if (Mips::GPR32RegClass.hasSubClassEq(RC))
264   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
266   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
268   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
270   else if (Mips::ACC128RegClass.hasSubClassEq(RC))
272   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
274   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
276   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
278   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
280   else if (RC->hasType(MVT::v16i8))
282   else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
284   else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
286   else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
288   else if (Mips::HI32RegClass.hasSubClassEq(RC))
290   else if (Mips::HI64RegClass.hasSubClassEq(RC))
292   else if (Mips::LO32RegClass.hasSubClassEq(RC))
294   else if (Mips::LO64RegClass.hasSubClassEq(RC))
458   const TargetRegisterClass *RC = STI.isABI_N64() ?
471   unsigned Reg = RegInfo.createVirtualRegister(RC);