Target/Mips/MipsSEISelLowering.cpp

38 MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
233   return new MipsSETargetLowering(TM, STI);
237 MipsSETargetLowering::getRepRegClassFor(MVT VT) const {
245 void MipsSETargetLowering::
294 void MipsSETargetLowering::
333 MipsSETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
360 SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
836                                  const MipsSETargetLowering *TL) {
1068 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1114 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1178 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1197 void MipsSETargetLowering::
1209 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1241 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1271 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1518 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
2186 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2254 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2293 SDValue MipsSETargetLowering::
2343 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2868 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2910 MachineBasicBlock * MipsSETargetLowering::
2973 MachineBasicBlock * MipsSETargetLowering::
3050 MachineBasicBlock * MipsSETargetLowering::
3093 MachineBasicBlock * MipsSETargetLowering::
3124 MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
3158 MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
3206 MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI,
3319 MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
3348 MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
3378 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI,
3407 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI,