ARM/AsmParser/ARMAsmParser.cpp

254   bool isThumbTwo() const {
4676       if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4683       if (!op.isSignedOffset<8, 1>() && isThumbTwo())
5417   if (isThumbTwo()) {
5511        (isThumbTwo() && Mnemonic == "sub")) &&
5524   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5551   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5571   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5945   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
6075   } else if (isThumbTwo() && MCID.isPredicable() &&
6220     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6224     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
6316         !isThumbTwo())
6326         !isThumbTwo())
6337     if (InvalidLowList && !isThumbTwo())
6355     if (!isThumbTwo() &&
8221       assert (isThumbTwo());
8240       assert (isThumbTwo());
8253     assert (isThumbTwo());
8264     assert (isThumbTwo());
8532     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8535     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&