Target/ARM/ARMLoadStoreOptimizer.cpp

89     bool isThumb1, isThumb2;
445   assert(isThumb1 && "Can only update base register uses for Thumb1!");
586   bool SafeToClobberCPSR = !isThumb1 ||
590   bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback.
595   if (isThumb1 && isi32Load(Opcode) && ContainsReg(Regs, Base)) {
607   bool haveIBAndDA = isNotVFP && !isThumb2 && !isThumb1;
613   } else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) {
647       NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass);
654       (isThumb1 && Base == ARM::SP) ? ARM::tADDrSPi :
655       (isThumb1 && Offset < 8) ? ARM::tADDi3 :
656       isThumb1 ? ARM::tADDi8  : ARM::ADDri;
662         (isThumb1 && Offset < 8 && Base != ARM::SP) ? ARM::tSUBi3 :
663         isThumb1 ? ARM::tSUBi8  : ARM::SUBri;
675     if (isThumb1) {
735   if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)
741     assert(isThumb1 && "expected Writeback only inThumb1");
1166   if (isThumb1) return false;
1273   if (isThumb1) return false;
1796   if (isThumb1) return false;
1863   isThumb1 = AFI->isThumbFunction() && !isThumb2;
1872     if (isThumb1)