Lines Matching defs:DCI

8411 // @param DCI     Context.
8416 TargetLowering::DAGCombinerInfo &DCI,
8418 SelectionDAG &DAG = DCI.DAG;
8442 TargetLowering::DAGCombinerInfo &DCI) {
8446 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
8451 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
8461 TargetLowering::DAGCombinerInfo &DCI,
8466 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
8520 SelectionDAG &DAG = DCI.DAG;
8559 TargetLowering::DAGCombinerInfo &DCI,
8565 if (DCI.isBeforeLegalize()) return SDValue();
8670 SelectionDAG &DAG = DCI.DAG;
8697 TargetLowering::DAGCombinerInfo &DCI,
8700 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
8709 TargetLowering::DAGCombinerInfo &DCI,
8713 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8719 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8728 TargetLowering::DAGCombinerInfo &DCI,
8734 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8739 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8745 TargetLowering::DAGCombinerInfo &DCI) {
8751 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8774 TargetLowering::DAGCombinerInfo &DCI,
8779 SelectionDAG &DAG = DCI.DAG;
8805 TargetLowering::DAGCombinerInfo &DCI,
8807 SelectionDAG &DAG = DCI.DAG;
8812 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8817 return PerformVMULCombine(N, DCI, Subtarget);
8884 DCI.CombineTo(N, Res, false);
8889 TargetLowering::DAGCombinerInfo &DCI,
8896 SelectionDAG &DAG = DCI.DAG;
8923 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8933 TargetLowering::DAGCombinerInfo &DCI,
8939 SelectionDAG &DAG = DCI.DAG;
8966 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
9061 DCI.CombineTo(N, Res, false);
9087 DCI.CombineTo(N, Res, false);
9103 DCI.CombineTo(N, Res, false);
9123 DCI.CombineTo(N, Res, false);
9130 TargetLowering::DAGCombinerInfo &DCI,
9133 SelectionDAG &DAG = DCI.DAG;
9140 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
9225 TargetLowering::DAGCombinerInfo &DCI) {
9242 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
9263 DCI.DAG.ReplaceAllUsesWith(CombineBFI, CombineBFI.getOperand(0));
9272 From1 = DCI.DAG.getNode(
9274 DCI.DAG.getConstant(NewFromMask.countTrailingZeros(), dl, VT));
9275 return DCI.DAG.getNode(ARMISD::BFI, dl, VT, N->getOperand(0), From1,
9276 DCI.DAG.getConstant(~NewToMask, dl, VT));
9284 TargetLowering::DAGCombinerInfo &DCI,
9289 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
9300 SelectionDAG &DAG = DCI.DAG;
9316 if (DCI.DAG.getDataLayout().isBigEndian())
9318 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
9360 TargetLowering::DAGCombinerInfo &DCI,
9366 SelectionDAG &DAG = DCI.DAG;
9385 DCI.AddToWorklist(V.getNode());
9394 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9447 SelectionDAG &DAG = DCI.DAG;
9473 DCI.AddToWorklist(V.getNode());
9480 DCI.AddToWorklist(Vec.getNode());
9487 TargetLowering::DAGCombinerInfo &DCI) {
9496 SelectionDAG &DAG = DCI.DAG;
9503 DCI.AddToWorklist(Vec.getNode());
9504 DCI.AddToWorklist(V.getNode());
9569 TargetLowering::DAGCombinerInfo &DCI) {
9570 SelectionDAG &DAG = DCI.DAG;
9765 DCI.CombineTo(N, NewResults);
9766 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9774 TargetLowering::DAGCombinerInfo &DCI) {
9775 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9778 return CombineBaseUpdate(N, DCI);
9785 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9786 SelectionDAG &DAG = DCI.DAG;
9848 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9857 DCI.CombineTo(VLD, VLDDupResults);
9865 TargetLowering::DAGCombinerInfo &DCI) {
9870 if (CombineVLDDUP(N, DCI))
9891 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
9895 TargetLowering::DAGCombinerInfo &DCI) {
9900 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
9901 return CombineBaseUpdate(N, DCI);
9909 TargetLowering::DAGCombinerInfo &DCI) {
9920 SelectionDAG &DAG = DCI.DAG;
10003 SelectionDAG &DAG = DCI.DAG;
10026 SelectionDAG &DAG = DCI.DAG;
10037 DCI.AddToWorklist(Vec.getNode());
10038 DCI.AddToWorklist(ExtElt.getNode());
10039 DCI.AddToWorklist(V.getNode());
10048 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
10049 return CombineBaseUpdate(N, DCI);
10648 DAGCombinerInfo &DCI) const {
10651 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
10652 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
10653 case ISD::SUB: return PerformSUBCombine(N, DCI);
10654 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
10655 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
10656 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
10657 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
10658 case ARMISD::BFI: return PerformBFICombine(N, DCI);
10659 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
10660 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
10661 case ISD::STORE: return PerformSTORECombine(N, DCI);
10662 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
10663 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
10664 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
10665 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
10668 return PerformVCVTCombine(N, DCI.DAG, Subtarget);
10670 return PerformVDIVCombine(N, DCI.DAG, Subtarget);
10671 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
10674 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
10677 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
10678 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
10679 case ISD::LOAD: return PerformLOADCombine(N, DCI);
10683 return PerformVLDCombine(N, DCI);
10685 return PerformARMBUILD_VECTORCombine(N, DCI);
10703 return PerformVLDCombine(N, DCI);