Target/ARM/ARMFrameLowering.cpp

41                         unsigned NumAlignedDPRCS2Regs);
894                                     unsigned NumAlignedDPRCS2Regs,
910       if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
968                                    unsigned NumAlignedDPRCS2Regs) const {
997       if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1061 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1066                                     unsigned NumAlignedDPRCS2Regs,
1080     if (DNum > NumAlignedDPRCS2Regs - 1)
1113                                   .addImm(8 * NumAlignedDPRCS2Regs)));
1134   // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1140   if (NumAlignedDPRCS2Regs >= 6) {
1150     NumAlignedDPRCS2Regs -= 4;
1158   if (NumAlignedDPRCS2Regs >= 4) {
1166     NumAlignedDPRCS2Regs -= 4;
1170   if (NumAlignedDPRCS2Regs >= 2) {
1177     NumAlignedDPRCS2Regs -= 2;
1181   if (NumAlignedDPRCS2Regs) {
1197                         unsigned NumAlignedDPRCS2Regs) {
1205   switch(NumAlignedDPRCS2Regs) {
1221 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1226                                       unsigned NumAlignedDPRCS2Regs,
1254   // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1258   if (NumAlignedDPRCS2Regs >= 6) {
1266     NumAlignedDPRCS2Regs -= 4;
1274   if (NumAlignedDPRCS2Regs >= 4) {
1281     NumAlignedDPRCS2Regs -= 4;
1285   if (NumAlignedDPRCS2Regs >= 2) {
1291     NumAlignedDPRCS2Regs -= 2;
1295   if (NumAlignedDPRCS2Regs)
1317   unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1323                NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1328   if (NumAlignedDPRCS2Regs)
1329     emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1344   unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1348   if (NumAlignedDPRCS2Regs)
1349     emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1355               NumAlignedDPRCS2Regs);