Lines Matching defs:Pred
168 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
182 .addImm(Pred).addReg(0).addReg(0);
189 .addImm(Pred).addReg(0).addReg(0);
194 .addImm(Pred).addReg(0).addReg(0);
205 .addImm(Pred).addReg(0).addReg(0);
210 .addImm(Pred).addReg(0).addReg(0);
220 .addReg(WBReg).addImm(0).addImm(Pred);
224 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
231 .addReg(BaseReg).addImm(0).addImm(Pred);
235 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
458 PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
463 .addImm(Pred[0].getImm())
464 .addReg(Pred[1].getReg());
471 PMO.setImm(Pred[0].getImm());
472 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
505 std::vector<MachineOperand> &Pred) const {
511 Pred.push_back(MO);
1710 MachineBasicBlock *Pred = *MBB.pred_begin();
1711 if (!Pred->empty()) {
1712 MachineInstr *LastMI = &*Pred->rbegin();
1715 if (CmpMI != Pred->begin()) {
1999 ARMCC::CondCodes Pred, unsigned PredReg,
2004 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
2026 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)