Target/AMDGPU/SIMachineScheduler.cpp

288 static bool isDefBetween(unsigned Reg,
293        UI = MRI->def_instr_begin(Reg),
330   for (unsigned Reg : RPTracker.getPressure().LiveInRegs) {
331     if (TargetRegisterInfo::isVirtualRegister(Reg))
332       LiveInRegs.insert(Reg);
336   // 1) Reg is not input to any instruction in the block, but is output of one
339   // 4) Reg is input of an instruction but another block will read it too
340   // 5) Reg is input of an instruction and then rewritten in the block.
342   // 6) Reg is input of an instruction and then rewritten in the block.
344   // 7) Reg is input of an instruction and then rewritten in the block.
357   for (unsigned Reg : RPTracker.getPressure().LiveOutRegs) {
358     if (TargetRegisterInfo::isVirtualRegister(Reg) &&
359         isDefBetween(Reg, LIS->getInstructionIndex(BeginBlock).getRegSlot(),
362       LiveOutRegs.insert(Reg);
575     for (unsigned Reg : LiveInRegs)
576       dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' ';
579     for (unsigned Reg : LiveOutRegs)
580       dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' ';
1188   DEBUG(dbgs() << "First phase: Fast scheduling for Reg Liveness\n");
1320     for (unsigned Reg : Block->getInRegs()) {
1325         std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg);
1340         LiveOutRegsNumUsages[PredID].find(Reg);
1342         ++LiveOutRegsNumUsages[PredID][Reg];
1344         LiveOutRegsNumUsages[PredID][Reg] = 1;
1373     for (unsigned Reg : Block->getInRegs()) {
1377         std::set<unsigned>::iterator RegPos = PredOutRegs.find(Reg);
1386         if (LiveRegsConsumers.find(Reg) == LiveRegsConsumers.end())
1387           LiveRegsConsumers[Reg] = 1;
1389           ++LiveRegsConsumers[Reg];
1480     for (unsigned Reg : LiveRegs)
1481       dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' ';
1540   for (unsigned Reg : Regs) {
1542     if (!TargetRegisterInfo::isVirtualRegister(Reg))
1545     (void) LiveRegs.insert(Reg);
1551   for (unsigned Reg : Regs) {
1553     std::set<unsigned>::iterator Pos = LiveRegs.find(Reg);
1554     assert (Pos != LiveRegs.end() && // Reg must be live.
1555                LiveRegsConsumers.find(Reg) != LiveRegsConsumers.end() &&
1556                LiveRegsConsumers[Reg] >= 1);
1557     --LiveRegsConsumers[Reg];
1558     if (LiveRegsConsumers[Reg] == 0)
1606   for (unsigned Reg : InRegs) {
1608     if (!TargetRegisterInfo::isVirtualRegister(Reg))
1610     if (LiveRegsConsumers[Reg] > 1)
1612     PSetIterator PSetI = DAG->getMRI()->getPressureSets(Reg);
1618   for (unsigned Reg : OutRegs) {
1620     if (!TargetRegisterInfo::isVirtualRegister(Reg))
1622     PSetIterator PSetI = DAG->getMRI()->getPressureSets(Reg);
1832     unsigned Reg = *RegI;
1834     if (!TargetRegisterInfo::isVirtualRegister(Reg))
1836     PSetIterator PSetI = MRI.getPressureSets(Reg);