Lines Matching defs:Reg
714 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
715 if (!Entry.isLiveIn(Reg))
716 Entry.addLiveIn(Reg);
854 unsigned Reg = MI->getOperand(0).getReg();
855 unsigned RegLo = TRI->getSubReg(Reg, AMDGPU::sub0);
856 unsigned RegHi = TRI->getSubReg(Reg, AMDGPU::sub1);
861 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
952 unsigned Reg = Src0.getReg();
959 Src1.ChangeToRegister(Reg, false);
1048 unsigned Reg, MachineRegisterInfo *MRI) const {
1049 if (!MRI->hasOneNonDBGUse(Reg))
1068 if (Src0->isReg() && Src0->getReg() == Reg) {
1119 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1127 if (Src2->isReg() && Src2->getReg() == Reg) {
1161 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1510 unsigned Reg = MI->getOperand(i).getReg();
1511 if (TargetRegisterInfo::isVirtualRegister(Reg))
1515 if (!RC->contains(Reg)) {
1656 unsigned Reg = MI.getOperand(OpNo).getReg();
1658 if (TargetRegisterInfo::isVirtualRegister(Reg))
1659 return MRI.getRegClass(Reg);
1660 return RI.getPhysRegClass(Reg);
1699 unsigned Reg = MRI.createVirtualRegister(VRC);
1701 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1703 MO.ChangeToRegister(Reg, false);
1774 unsigned Reg = MO.getReg();
1776 TargetRegisterInfo::isVirtualRegister(Reg) ?
1777 MRI.getRegClass(Reg) :
1778 RI.getPhysRegClass(Reg);
2952 unsigned Reg = MO.getReg();
2953 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
2955 UsedSGPRs[i] = Reg;