Target/AMDGPU/SIISelLowering.cpp

39 SITargetLowering::SITargetLowering(TargetMachine &TM,
294 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
301 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
307 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
342 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
433 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
475 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
501 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
507 bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
522 SITargetLowering::getPreferredVectorAction(EVT VT) const {
529 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
536 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
571 SDValue SITargetLowering::LowerFormalArguments(
890 SDValue SITargetLowering::LowerReturn(SDValue Chain,
981 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
993 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1004 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
1012 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {
1031 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
1057 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1103 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
1132 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
1207 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
1223 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL,
1240 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
1252 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
1401 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1447 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1485 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
1494 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
1523 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1562 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1604 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1671 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1683 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1710 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1734 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1880 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
1913 SDValue SITargetLowering::performAndCombine(SDNode *N,
1967 SDValue SITargetLowering::performOrCombine(SDNode *N,
1997 SDValue SITargetLowering::performClassCombine(SDNode *N,
2030 SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
2066 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
2097 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
2275 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
2313 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
2402 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
2422 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
2440 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
2491 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
2527 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
2559 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2573 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2632 SITargetLowering::ConstraintType
2633 SITargetLowering::getConstraintType(StringRef Constraint) const {