Target/AMDGPU/R600InstrInfo.cpp

1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
15 #include "R600InstrInfo.h"
31 R600InstrInfo::R600InstrInfo(const AMDGPUSubtarget &st)
34 const R600RegisterInfo &R600InstrInfo::getRegisterInfo() const {
38 bool R600InstrInfo::isTrig(const MachineInstr &MI) const {
42 bool R600InstrInfo::isVector(const MachineInstr &MI) const {
47 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
82 bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
93 bool R600InstrInfo::isMov(unsigned Opcode) const {
108 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const {
116 bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
120 bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
131 bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
137 bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
145 bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
153 bool R600InstrInfo::isLDSNoRetInstr(unsigned Opcode) const {
157 bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const {
161 bool R600InstrInfo::canBeConsideredALU(const MachineInstr *MI) const {
179 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
185 bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const {
189 bool R600InstrInfo::isVectorOnly(unsigned Opcode) const {
193 bool R600InstrInfo::isVectorOnly(const MachineInstr *MI) const {
197 bool R600InstrInfo::isExport(unsigned Opcode) const {
201 bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
205 bool R600InstrInfo::usesVertexCache(const MachineInstr *MI) const {
212 bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
216 bool R600InstrInfo::usesTextureCache(const MachineInstr *MI) const {
224 bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
234 bool R600InstrInfo::usesAddressRegister(MachineInstr *MI) const {
238 bool R600InstrInfo::definesAddressRegister(MachineInstr *MI) const {
242 bool R600InstrInfo::readsLDSSrcReg(const MachineInstr *MI) const {
258 int R600InstrInfo::getSrcIdx(unsigned Opcode, unsigned SrcNum) const {
269 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
293 R600InstrInfo::getSrcs(MachineInstr *MI) const {
353 R600InstrInfo::ExtractSrcs(MachineInstr *MI,
387         R600InstrInfo::BankSwizzle Swz) {
391   case R600InstrInfo::ALU_VEC_012_SCL_210:
393   case R600InstrInfo::ALU_VEC_021_SCL_122:
396   case R600InstrInfo::ALU_VEC_102_SCL_221:
399   case R600InstrInfo::ALU_VEC_120_SCL_212:
403   case R600InstrInfo::ALU_VEC_201:
407   case R600InstrInfo::ALU_VEC_210:
415 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
417   case R600InstrInfo::ALU_VEC_012_SCL_210: {
421   case R600InstrInfo::ALU_VEC_021_SCL_122: {
425   case R600InstrInfo::ALU_VEC_120_SCL_212: {
429   case R600InstrInfo::ALU_VEC_102_SCL_221: {
442 unsigned  R600InstrInfo::isLegalUpTo(
444     const std::vector<R600InstrInfo::BankSwizzle> &Swz,
446     R600InstrInfo::BankSwizzle TransSwz) const {
457         if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
458             Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
493     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
497   while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
500     SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
505   SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
511 bool R600InstrInfo::FindSwizzleForVectorSlot(
513     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
515     R600InstrInfo::BankSwizzle TransSwz) const {
528 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
548 R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
563     ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
574   static const R600InstrInfo::BankSwizzle TransSwz[] = {
597 R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
622 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
653 R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const {
692 R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
776 R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
822 R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
880 R600InstrInfo::isPredicated(const MachineInstr *MI) const {
896 R600InstrInfo::isPredicable(MachineInstr *MI) const {
922 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
930 R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
941 R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
949 R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
956 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
990 R600InstrInfo::DefinesPredicate(MachineInstr *MI,
997 R600InstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1004 R600InstrInfo::PredicateInstruction(MachineInstr *MI,
1038 unsigned int R600InstrInfo::getPredicationCost(const MachineInstr *) const {
1042 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1050 bool R600InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1073 void  R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1094 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
1101 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
1105 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1112 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1137 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1144 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1171 unsigned R600InstrInfo::getMaxAlusPerClause() const {
1175 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
1254 MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
1302 MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
1312 MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB,
1318 int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
1322 int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
1326 void R600InstrInfo::setImmOperand(MachineInstr *MI, unsigned Op,
1338 bool R600InstrInfo::hasFlagOperand(const MachineInstr &MI) const {
1342 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr *MI, unsigned SrcIdx,
1397 void R600InstrInfo::addFlag(MachineInstr *MI, unsigned Operand,
1418 void R600InstrInfo::clearFlag(MachineInstr *MI, unsigned Operand,