Target/AMDGPU/R600ISelLowering.cpp

198     MachineInstr * MI, MachineBasicBlock * BB) const {
201   MachineBasicBlock::iterator I = *MI;
205   switch (MI->getOpcode()) {
209     if (TII->isLDSRetInstr(MI->getOpcode())) {
210       int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
215       if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()) ||
216            MI->getOpcode() == AMDGPU::LDS_CMPST_RET)
220                       TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
221       for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
222         NewMI.addOperand(MI->getOperand(i));
225       return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
231                                                    MI->getOperand(0).getReg(),
232                                                    MI->getOperand(1).getReg());
240                                                     MI->getOperand(0).getReg(),
241                                                     MI->getOperand(1).getReg());
249                                                     MI->getOperand(0).getReg(),
250                                                     MI->getOperand(1).getReg());
256     unsigned maskedRegister = MI->getOperand(0).getReg();
264     TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
265                      MI->getOperand(1).getFPImm()->getValueAPF()
269     TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
270                      MI->getOperand(1).getImm());
273     MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
274         MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
276         MI->getOperand(1).getImm());
283     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
284             .addOperand(MI->getOperand(0))
285             .addOperand(MI->getOperand(1))
290     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
291             .addOperand(MI->getOperand(0))
292             .addOperand(MI->getOperand(1))
293             .addOperand(MI->getOperand(2))
301     MachineOperand &RID = MI->getOperand(4);
302     MachineOperand &SID = MI->getOperand(5);
303     unsigned TextureId = MI->getOperand(6).getImm();
337             .addOperand(MI->getOperand(3))
356             .addOperand(MI->getOperand(2))
375             .addOperand(MI->getOperand(0))
376             .addOperand(MI->getOperand(1))
402     MachineOperand &RID = MI->getOperand(4);
403     MachineOperand &SID = MI->getOperand(5);
404     unsigned TextureId = MI->getOperand(6).getImm();
439             .addOperand(MI->getOperand(3))
458             .addOperand(MI->getOperand(2))
477             .addOperand(MI->getOperand(0))
478             .addOperand(MI->getOperand(1))
503               .addOperand(MI->getOperand(0));
510               .addOperand(MI->getOperand(1))
515             .addOperand(MI->getOperand(0))
524             .addOperand(MI->getOperand(1))
529            .addOperand(MI->getOperand(0))
538     unsigned InstExportType = MI->getOperand(1).getImm();
555     unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
556     BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
557             .addOperand(MI->getOperand(0))
558             .addOperand(MI->getOperand(1))
559             .addOperand(MI->getOperand(2))
560             .addOperand(MI->getOperand(3))
561             .addOperand(MI->getOperand(4))
562             .addOperand(MI->getOperand(5))
563             .addOperand(MI->getOperand(6))
572     MachineInstrBuilder MIB(*MF, MI);
579   MI->eraseFromParent();