AArch64/InstPrinter/AArch64InstPrinter.cpp

662       unsigned Reg = MI->getOperand(OpNum++).getReg();
663       if (Reg != AArch64::XZR)
664         O << ", " << getRegisterName(Reg);
913     unsigned Reg = MI->getOperand(4).getReg();
917       O << ", " << getRegisterName(Reg);
928     unsigned Reg = Op.getReg();
929     O << getRegisterName(Reg);
949     unsigned Reg = Op.getReg();
950     if (Reg == AArch64::XZR)
953       O << getRegisterName(Reg);
963   unsigned Reg = Op.getReg();
964   O << getRegisterName(Reg, AArch64::vreg);
1172 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1174     switch (Reg) {
1177     case AArch64::Q0:  Reg = AArch64::Q1;  break;
1178     case AArch64::Q1:  Reg = AArch64::Q2;  break;
1179     case AArch64::Q2:  Reg = AArch64::Q3;  break;
1180     case AArch64::Q3:  Reg = AArch64::Q4;  break;
1181     case AArch64::Q4:  Reg = AArch64::Q5;  break;
1182     case AArch64::Q5:  Reg = AArch64::Q6;  break;
1183     case AArch64::Q6:  Reg = AArch64::Q7;  break;
1184     case AArch64::Q7:  Reg = AArch64::Q8;  break;
1185     case AArch64::Q8:  Reg = AArch64::Q9;  break;
1186     case AArch64::Q9:  Reg = AArch64::Q10; break;
1187     case AArch64::Q10: Reg = AArch64::Q11; break;
1188     case AArch64::Q11: Reg = AArch64::Q12; break;
1189     case AArch64::Q12: Reg = AArch64::Q13; break;
1190     case AArch64::Q13: Reg = AArch64::Q14; break;
1191     case AArch64::Q14: Reg = AArch64::Q15; break;
1192     case AArch64::Q15: Reg = AArch64::Q16; break;
1193     case AArch64::Q16: Reg = AArch64::Q17; break;
1194     case AArch64::Q17: Reg = AArch64::Q18; break;
1195     case AArch64::Q18: Reg = AArch64::Q19; break;
1196     case AArch64::Q19: Reg = AArch64::Q20; break;
1197     case AArch64::Q20: Reg = AArch64::Q21; break;
1198     case AArch64::Q21: Reg = AArch64::Q22; break;
1199     case AArch64::Q22: Reg = AArch64::Q23; break;
1200     case AArch64::Q23: Reg = AArch64::Q24; break;
1201     case AArch64::Q24: Reg = AArch64::Q25; break;
1202     case AArch64::Q25: Reg = AArch64::Q26; break;
1203     case AArch64::Q26: Reg = AArch64::Q27; break;
1204     case AArch64::Q27: Reg = AArch64::Q28; break;
1205     case AArch64::Q28: Reg = AArch64::Q29; break;
1206     case AArch64::Q29: Reg = AArch64::Q30; break;
1207     case AArch64::Q30: Reg = AArch64::Q31; break;
1210       Reg = AArch64::Q0;
1214   return Reg;
1224   unsigned Reg = MI->getOperand(OpNum).getReg();
1229   unsigned Even = MRI.getSubReg(Reg,  Sube);
1230   unsigned Odd = MRI.getSubReg(Reg,  Subo);
1238   unsigned Reg = MI->getOperand(OpNum).getReg();
1245   if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1246       MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
1248   else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1249            MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1251   else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1252            MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
1256   if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1257     Reg = FirstReg;
1258   else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1259     Reg = FirstReg;
1263   if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1266     Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1269   for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1270     O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;