Target/AArch64/AArch64LoadStoreOptimizer.cpp

1013   MachineInstr *FirstMI = I;
1014   unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
1036     if (MI->mayStore() && isMatchingStore(FirstMI, MI) &&
1038         isLdOffsetInRangeOfSt(FirstMI, MI) &&
1056     if (MI->mayStore() && mayAlias(FirstMI, MI, TII))
1069   MachineInstr *FirstMI = I;
1072   unsigned Opc = FirstMI->getOpcode();
1073   bool MayLoad = FirstMI->mayLoad();
1074   bool IsUnscaled = isUnscaledLdSt(FirstMI);
1075   unsigned Reg = getLdStRegOp(FirstMI).getReg();
1076   unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
1077   int Offset = getLdStOffsetOp(FirstMI).getImm();
1086   if (FirstMI->modifiesRegister(BaseReg, TRI))
1092   int OffsetStride = IsUnscaled ? getMemScale(FirstMI) : 1;
1103   // Remember any instructions that read/write memory between FirstMI and MI.
1207         if (!ModifiedRegs[getLdStRegOp(FirstMI).getReg()] &&
1208             !(MayLoad && UsedRegs[getLdStRegOp(FirstMI).getReg()]) &&
1209             !mayAlias(FirstMI, MemInsns, TII)) {